參數(shù)資料
型號: AD9824KCPZRL
廠商: Analog Devices Inc
文件頁數(shù): 3/24頁
文件大小: 0K
描述: IC CCD SIGNAL PROC 14BIT 48LFCSP
標(biāo)準(zhǔn)包裝: 2,500
類型: CCD 信號處理器,14 位
輸入類型: 邏輯
輸出類型: 邏輯
接口: 3 線串口
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 48-LFCSP-VQ(7x7)
包裝: 帶卷 (TR)
REV. 0
AD9824
–11–
HD
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2
012012012...
...01201
VD
LINE N
LINE N+1
Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN1
VD
GAIN2
GAIN0
GAIN1
GAIN0
GAINX
GAIN0
GAINX
3ns MIN
5 PIXEL MIN
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.
Figure 13. PxGA Mode 3 (3-Color) Detailed Timing
VD
HD
*0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3
LINE N
LINE N+1
012301230123...
...01230
01230123012...
Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence
SHP
HD
5 PIXEL MIN
PxGA GAIN
GAIN1
VD
GAIN2
GAIN0
GAIN1
GAIN0
GAINX
GAIN0
GAINX
3ns MIN
5 PIXEL MIN
NOTES
1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.
2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.
Figure 15. PxGA Mode 4 (4-Color) Detailed Timing
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