參數(shù)資料
型號(hào)： AD9653-125EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 32/40頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9653
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 16
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，串行，SPI?
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 673mW @ 125MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9653
已供物品： 板
AD9653
Data Sheet
Rev. 0 | Page 38 of 40
Output Phase (Register 0x16)
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
Table 21. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
Number of Input Clock Cycles of
Phase Delay
000 (Default)
0
001
1
010
2
011
3
100
4
101
5
110
6
111
7
Bits[3:0]—Output Clock Phase Adjust
Table 22. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
DCO Phase Adjustment (Degrees
Relative to D0±x/D1±x Edge)
0000
0
0001
60
0010
120
0011 (Default)
180
0100
240
0101
300
0110
360
0111
420
1000
480
1001
540
1010
600
1011
660
Serial Output Data Control (Register 0x21)
The serial output data control register is used to program the
AD9653 in various output data modes depending upon the data
capture solution. Table 23 describes the various serialization
options available in the AD9653.
Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the sample
rate. Settings in this register are not initialized until Bit 0 of the
transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit the loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
Table 23. SPI Register Options
Serialization Options Selected
Register 0x21
Contents
Serial Output Number
of Bits (SONB)
Frame Mode
Serial Data Mode
DCO Multiplier
Timing Diagram
0x30
16-bit
1×
DDR two-lane, bytewise
4 × fS
Figure 2 (default setting)
0x20
16-bit
1×
DDR two-lane, bitwise
4 × fS
0x10
16-bit
1×
SDR two-lane, bytewise
8 × fS
0x00
16-bit
1×
SDR two-lane, bitwise
8 × fS
0x34
16-bit
2×
DDR two-lane, bytewise
4 × fS
0x24
16-bit
2×
DDR two-lane, bitwise
4 × fS
0x14
16-bit
2×
SDR two-lane, bytewise
8 × fS
0x04
16-bit
2×
SDR two-lane, bitwise
8 × fS
0x40
16-bit
1×
DDR one-lane, wordwise
8 × fS
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