參數(shù)資料
型號(hào)： AD9653-125EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 27/40頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD9653
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 4
位數(shù)： 16
采樣率（每秒）： 125M
數(shù)據(jù)接口： LVDS，串行，SPI?
輸入范圍： 2 Vpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 673mW @ 125MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9653
已供物品： 板
Data Sheet
AD9653
Rev. 0 | Page 33 of 40
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit locations.
The memory map is roughly divided into three sections: the chip
configuration registers (Address 0x00 to Address 0x02); the device
index and transfer registers (Address 0x05 and Address 0xFF);
and the global ADC functions registers, including setup, control,
and test (Address 0x08 to Address 0x109).
The memory map register table (see Table 19) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI. This application note details the functions
controlled by Register 0x00 to Register 0xFF. The remaining
registers are documented in the Memory Map Register
Open Locations
All address and bit locations that are not included in Table 19
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Table 19 (for example, Address 0x13), this
address location should not be written.
Default Values
After the AD9653 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 19.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in
Table 19 as local. These local registers and bits can be accessed
by setting the appropriate data channel bits (A, B, C, or D) and
the clock channel DCO bit (Bit 5) and FCO bit (Bit 4) in
Register 0x05. If all the bits are set, the subsequent write affects
the registers of all channels and the DCO/FCO clock channels.
In a read cycle, only one of the channels (A, B, C, or D) should
be set to read one of the four registers. If all the bits are set
during a SPI read cycle, the part returns the value for Channel A.
Registers and bits designated as global in Table 19 affect the
entire part or the channel features for which independent
settings are not allowed between channels. The settings in
Register 0x05 do not affect the global registers and bits.
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