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參數(shù)資料
| 型號(hào)： | AD9653-125EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD9653 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| ADC 的數(shù)量： | 4 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | LVDS，串行，SPI? |
| 輸入范圍： | 2 Vpp |
| 在以下條件下的電源（標(biāo)準(zhǔn)）： | 673mW @ 125MSPS |
| 工作溫度： | -40°C ~ 85°C |
| 已用 IC / 零件： | AD9653 |
| 已供物品： | 板 |
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AD9653
Data Sheet
Rev. 0 | Page 32 of 40
HARDWARE INTERFACE
The pins described in Table 17 comprise the physical interface
between the user programming device and the serial port of the
AD9653. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note, Micro-
controller-Based Serial Port Interface (SPI) Boot Circuit.
The SPI port should not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used for
other devices, it may be necessary to provide buffers between
this bus and the AD9653 to prevent these signals from transi-
tioning at the converter inputs during critical sampling periods.
Some pins serve a dual function when the SPI interface is not
being used. When the pins are strapped to DRVDD or ground
during device power-on, they are associated with a specific
function. Table 15 and Table 16 describe the strappable
functions supported on the AD9653.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/OLM pin, the SCLK/DTP pin, and the PDWN pin
serve as standalone CMOS-compatible control pins. When the
device is powered up, it is assumed that the user intends to use the
pins as static control lines for the output lane mode, digital test
pattern, and power-down feature control. In this mode, CSB
should be connected to AVDD, which disables the serial port
interface.
Note that, when the CSB pin is tied to AVDD, the AD9653 DCS
is on by default and remains on unless the part is placed in SPI
mode and controlled via the SPI. Refer to the Clock Duty Cycle
section for more information on the DCS.
When the device is in SPI mode, the PDWN pin (if enabled)
remains active. For SPI control of power-down, the PDWN pin
should be set to its default state.
SPI ACCESSIBLE FEATURES
Table 18 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note, Interfacing to High Speed ADCs
via SPI. The AD9653 part-specific features are described in detail
following Table 19, the external memory map register table.
Table 18. Features Accessible Using the SPI
Feature Name
Description
Power Mode
Allows the user to set either power-down mode
or standby mode
Clock
Allows the user to set the clock divider, set the
clock divider phase, and enable the sync
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set test modes to have
known data on output bits
Output Mode
Allows the user to set the output mode
Output Phase
Allows the user to set the output clock polarity
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