- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1981 > AD7451BRMZ (Analog Devices Inc)IC ADC 12BIT DIFF 1MSPS 8MSOP PDF資料下載
參數(shù)資料
| 型號： | AD7451BRMZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DIFF 1MSPS 8MSOP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 9.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-MSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
AD7441/AD7451
Rev. D | Page 7 of 24
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min
18
MHz max
tCONVERT
16 × tSCLK
tSCLK = 1/fSCLK
888
ns max
tQUIET
60
ns min
Minimum quiet time between end of a serial read and next falling edge of CS
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS falling edge to SCLK falling edge setup time
20
ns max
Delay from CS falling edge until SDATA three-state disabled
t4
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK high pulse width
t6
0.4 tSCLK
ns min
SCLK low pulse width
t7
10
ns min
SCLK edge to data valid hold time
10
ns min
SCLK falling edge to SDATA, three-state enabled
35
ns max
SCLK falling edge to SDATA, three-state enabled
tPOWER-UP5
1
μs max
Power-up time from full power-down
1 Guaranteed by characterization. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,
and the Serial Interface section.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to
cross 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See the Power-Up Time section.
TIMING DIAGRAMS
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
THREE-STATE
12
3
4
5
13
14
15
16
0
DB11
DB10
DB2
DB1
DB0
B
03
15
3-
0
02
Figure 2. AD7451 Serial Interface Timing Diagram
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
2 TRAILING ZEROS THREE-STATE
12
3
4
5
13
14
15
16
0
DB9
DB8
DB0
0
B
03
15
3-
0
03
Figure 3. AD7441 Serial Interface Timing Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7452BRT-R2 | IC ADC 12BIT 555KSPS SOT23-8 |
| AD7453BRTZ-REEL7 | IC ADC 12BIT W/DIFF INP SOT23-8 |
| AD7457BRTZ-REEL7 | IC ADC 12BIT PSEUDO-DIFF SOT23-8 |
| AD7467BRTZ-REEL | IC ADC 10BIT 1.6V MCRPWR SOT23-6 |
| AD7472ARU-REEL | IC ADC 12BIT PARALLEL 24-TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7451BRMZ | 制造商:Analog Devices 功能描述:12BIT SAR ADC DIFF I/P SMD 7451 |
| AD7451BRT | 制造商:AD 制造商全稱:Analog Devices 功能描述:Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23 |
| AD7451BRT-R2 | 功能描述:IC ADC 12BIT W/DIFF INP SOT-23-8 RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):12 采樣率（每秒）:3M 數(shù)據(jù)接口:- 轉(zhuǎn)換器數(shù)目:- 功率耗散（最大）:- 電壓電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:SOT-23-6 供應(yīng)商設(shè)備封裝:SOT-23-6 包裝:帶卷 (TR) 輸入數(shù)目和類型:- |
| AD7451BRT-REEL7 | 制造商:Analog Devices 功能描述: |
| AD7452 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Differential Input, 555 kSPS 12-Bit ADC in an 8-Lead SOT-23 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。