- 鎮ㄧ従鍦ㄧ殑浣嶇疆锛�璨疯常IC缍� > PDF鐩寗1981 > AD7451BRMZ (Analog Devices Inc)IC ADC 12BIT DIFF 1MSPS 8MSOP PDF璩囨枡涓嬭級
鍙冩暩璩囨枡
| 鍨嬭櫉锛� | AD7451BRMZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩锛� | 24/25闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT DIFF 1MSPS 8MSOP |
| 妯欐簴鍖呰锛� | 50 |
| 浣嶆暩锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁告摎鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? |
| 杞夋彌鍣ㄦ暩鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 9.25mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁哥洰鍜岄鍨嬶細 | 1 鍊嬪伣宸垎锛屽柈妤� |
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AD7441/AD7451
Rev. D | Page 7 of 24
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min
18
MHz max
tCONVERT
16 脳 tSCLK
tSCLK = 1/fSCLK
888
ns max
tQUIET
60
ns min
Minimum quiet time between end of a serial read and next falling edge of CS
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS falling edge to SCLK falling edge setup time
20
ns max
Delay from CS falling edge until SDATA three-state disabled
t4
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK high pulse width
t6
0.4 tSCLK
ns min
SCLK low pulse width
t7
10
ns min
SCLK edge to data valid hold time
10
ns min
SCLK falling edge to SDATA, three-state enabled
35
ns max
SCLK falling edge to SDATA, three-state enabled
tPOWER-UP5
1
渭s max
Power-up time from full power-down
1 Guaranteed by characterization. All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,
and the Serial Interface section.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to
cross 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See the Power-Up Time section.
TIMING DIAGRAMS
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
THREE-STATE
12
3
4
5
13
14
15
16
0
DB11
DB10
DB2
DB1
DB0
B
03
15
3-
0
02
Figure 2. AD7451 Serial Interface Timing Diagram
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
2 TRAILING ZEROS THREE-STATE
12
3
4
5
13
14
15
16
0
DB9
DB8
DB0
0
B
03
15
3-
0
03
Figure 3. AD7441 Serial Interface Timing Diagram
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鐩搁棞浠ｇ悊鍟�/鎶€琛撳弮鏁� |
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