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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7451BRMZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 22/25闋�(y猫) |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 12BIT DIFF 1MSPS 8MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 9.25mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊�(g猫)鍋藉樊鍒�锛屽柈妤� |
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)鐣�(d膩ng)鍓嶇22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)
AD7441/AD7451
Rev. D | Page 5 of 24
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for
B version: 40掳C to +85掳C.
Table 2. AD7441
Parameter
Test Conditions/Comments
B Version
Unit
DYNAMIC PERFORMANCE
fIN = 100 kHz
Signal-to-(Noise + Distortion) (SINAD)1
61
dB min
Total Harmonic Distortion (THD)1
2.7 V to 3.6 V; 77 dB typical
72
dB max
4.75 V to 5.25 V; 79 dB typical
73
dB max
Peak Harmonic or Spurious Noise1
2.7 V to 3.6 V; 80 dB typical
72
dB max
4.75 V to 5.25 V; 82 dB typical
74
dB max
Intermodulation Distortion (IMD)1
fa = 90 kHz, fb = 110 kHz
Second-Order Terms
80
dB typ
Third-Order Terms
80
dB typ
Aperture Delay1
5
ns typ
Aperture Jitter1
50
ps typ
Full-Power Bandwidth1, 2
@ 3 dB
20
MHz typ
@ 0.1 dB
2.5
MHz typ
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity (INL)1
卤0.5
LSB max
Differential Nonlinearity (DNL)1
Guaranteed no missed codes to 10 bits
卤0.5
LSB max
Offset Error1
卤1
LSB max
Gain Error1
卤1
LSB max
ANALOG INPUT
Full-Scale Input Span
VIN+ VIN鈥�
VREF
V
Absolute Input Voltage
VIN+
VREF
V
VDD = 2.7 V to 3.6 V
0.1 to +0.4
V
VDD = 4.75 V to 5.25 V
0.1 to +1.5
V
DC Leakage Current
卤1
渭A max
Input Capacitance
When in track-and-hold
30/10
pF typ
REFERENCE INPUT
卤1% tolerance for specified performance
2.5
V
DC Leakage Current
卤1
渭A max
VREF Input Capacitance
When in track-and-hold
10/30
pF typ
LOGIC INPUTS
Input High Voltage, VINH
2.4
V min
Input Low Voltage, VINL
0.8
V max
Input Current, IIN
Typically 10 nA, VIN = 0 V or VDD
卤1
渭A max
Input Capacitance, CIN5
10
pF max
LOGIC OUTPUTS
Output High Voltage, VOH
VDD = 4.75 V to 5.25 V; ISOURCE = 200 渭A
2.8
V min
VDD = 2.7 V to 3.6 V; ISOURCE = 200 渭A
2.4
V min
Output Low Voltage, VOL
ISINK = 200 渭A
0.4
V max
Floating-State Leakage Current
卤1
渭A max
Floating-State Output Capacitance5
10
pF max
Output Coding
Straight (natural) binary
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