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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD7451BRMZ
寤犲晢锛� Analog Devices Inc
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鎻忚堪锛� IC ADC 12BIT DIFF 1MSPS 8MSOP
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渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-MSOP
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AD7441/AD7451
Rev. D | Page 9 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD
SCLK
SDATA
CS
8
7
6
5
VREF 1
VIN+ 2
VIN鈥� 3
GND 4
AD7441/
AD7451
TOP VIEW
(Not to Scale)
0
31
53
-00
6
Figure 5. 8-Lead MSOP Pin Configuration
VREF
VIN+
VIN鈥�
GND
8
7
6
5
VDD 1
SCLK 2
SDATA 3
CS 4
AD7441/
AD7451
TOP VIEW
(Not to Scale)
0
31
53
-00
5
Figure 6. 8-Lead SOT-23 Pin Configuration
Table 5. Pin Function Descriptions
Pin. No.
Mnemonic
Description
MSOP
SOT-23
1
8
VREF
Reference Input for the AD7441/AD7451. An external reference in the range of 100 mV to VDD must be
applied to this input. The specified reference input is 2.5 V. This pin is decoupled to GND with a capacitor
of at least 0.1 渭F.
2
7
VIN+
Noninverting Analog Input.
3
6
VIN鈥�
Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc
offset to provide a pseudo ground.
4
5
GND
Analog Ground. Ground reference point for all circuitry on the AD7441/AD7451. All analog input signals
and any external reference signal are referred to this GND voltage.
5
4
CS
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on
the AD7441/AD7451 and framing the serial data transfer.
6
3
SDATA
Serial Data, Logic Output. The conversion result from the AD7441/AD7451 is provided on this output as
a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of
the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided
MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of con-
version data, followed by two trailing zeros. In both cases, the output coding is straight (natural) binary.
7
2
SCLK
Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input
is also used as the clock source for the conversion process.
8
1
VDD
Power Supply Input. VDD is 2.7 V to 5.25 V. This supply is decoupled to GND with a 0.1 渭F capacitor and a
10 渭F tantalum capacitor.
鐩搁棞(gu膩n)PDF璩囨枡
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