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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7451BRMZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 10/25闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC ADC 12BIT DIFF 1MSPS 8MSOP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 浣嶆暩(sh霉)锛� | 12 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 1M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 9.25mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊�(g猫)鍋藉樊鍒�锛屽柈妤� |
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AD7441/AD7451
Rev. D | Page 17 of 24
Timing Example 2
Timing Example 1
Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 渭s
1/Throughput = 1/1,000,000 = 1 渭s
A cycle consists of
t2 + 12.5 (1/fSCLK) + tACQUISITION = 3.174 渭s
t2 + 12.5 (1/fSCLK) + tACQUISITION = 1 渭s
Therefore, if t2 is 10 ns, then
Therefore, if t2 = 10 ns, then
10 ns + 12.5 (1/5 MHz) + tACQUISITION = 3.174 渭s
tACQUISITION = 664 ns
10 ns + 12.5 (1/18 MHz) + tACQUISITION = 1 渭s
tACQUISITION = 296 ns
This 664 ns satisfies the requirement of 290 ns for tACQUISITION.
This 296 ns satisfies the requirement of 290 ns for tACQUISITION.
2.5 (1/fSCLK) + t8 = tQUIET
where t8 = 35 ns. This allows a value of 129 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
where t8 = 35 ns. This allows a value of 122 ns for tQUIET,
satisfying the minimum requirement of 60 ns.
As in this example and with other slower clock values, the signal
can already be acquired before the conversion is complete, but it
is still necessary to leave 60 ns minimum tQUIET between conver-
sions. In Example 2, the signal is fully acquired at approximately
Point C in Figure 28.
t2
t8
t6
t5
tCONVERT
CS
SCLK
12
3
4
5
13
14
15
16
12.5(1/
fSCLK)
tACQUISITION
1/THROUGHPUT
tQUIET
10ns
B
C
03
15
3-
02
8
Figure 28. Serial Interface Timing Example
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| AD7457BRTZ-REEL7 | IC ADC 12BIT PSEUDO-DIFF SOT23-8 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7451BRMZ | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:12BIT SAR ADC DIFF I/P SMD 7451 |
| AD7451BRT | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:Pseudo Differential, 1MSPS, 12- & 10-Bit ADCs in 8-lead SOT-23 |
| AD7451BRT-R2 | 鍔熻兘鎻忚堪:IC ADC 12BIT W/DIFF INP SOT-23-8 RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 浣嶆暩(sh霉):12 閲囨ǎ鐜囷紙姣忕锛�:3M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:- 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:- 鍔熺巼鑰楁暎锛堟渶澶э級:- 闆诲闆绘簮:- 宸ヤ綔婧害:- 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:SOT-23-6 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:SOT-23-6 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:- |
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