TIMING CHARACTERISTICS (C LOAD = 40 pF All Ou" />
參數(shù)資料
型號： AD6620ASZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/44頁
文件大?。?/td> 0K
描述： IC DGTL RCVR DUAL 67MSPS 80-PQFP
標(biāo)準包裝： 1
接口： 并行/串行
電源電壓： 3 V ~ 3.6 V
封裝/外殼： 80-BQFP
供應(yīng)商設(shè)備封裝： 80-PQFP（14x14）
包裝： 托盤
安裝類型： 表面貼裝
產(chǎn)品目錄頁面： 551 (CN2011-ZH PDF)
–5–
REV. A
AD6620
TIMING CHARACTERISTICS (C
LOAD = 40 pF All Outputs)
Test
AD6620AS
Parameter (Conditions)
Temp
Level
Min
Typ
Max
Unit
CLK Timing Requirements:
tCLK
CLK Period
Full
I
14.93
1
ns
tCLK
CLK Period
Full
I
15.4
ns
tCLKL
CLK Width Low
Full
IV
7.0
0.5
× t
CLK
ns
tCLKH
CLK Width High
Full
IV
7.0
0.5
× tCLK
ns
Reset Timing Requirements:
tRESL
RESET Width Low
Full
I
30.0
ns
Input Data Timing Requirements:
tSI
Input
2 to CLK Setup Time
Full
IV
–1.0
ns
tHI
Input
2 to CLK Hold Time
Full
IV
6.5
ns
Parallel Output Switching Characteristics:
tDPR
CLK to OUT[15:0] Rise Delay
Full
IV
8.0
19.5
ns
tDPF
CLK to OUT[15:0] Fall Delay
Full
IV
7.5
19.5
ns
tDPR
CLK to DVOUT Rise Delay
Full
IV
6.5
19.0
ns
tDPF
CLK to DVOUT Fall Delay
Full
IV
5.5
11.5
ns
tDPR
CLK to IQOUT Rise Delay
Full
IV
7.0
19.5
ns
tDPF
CLK to IQOUT Fall Delay
Full
IV
6.0
13.5
ns
tDPR
CLK to ABOUT Rise Delay
Full
IV
7.0
19.5
ns
tDPF
CLK to ABOUT Fall Delay
Full
IV
5.5
13.5
ns
SYNC Timing Requirements:
tSY
SYNC
3 to CLK Setup Time
Full
IV
–1.0
ns
tHY
SYNC
3 to CLK Hold Time
Full
IV
6.5
ns
SYNC Switching Characteristics:
tDY
CLK to SYNC
4 Delay Time
Full
V
7.0
23.5
ns
Serial Input Timing:
tSSI
SDI to SCLK
t Setup Time
Full
IV
1.0
ns
tHSI
SDI to SCLK
t Hold Time
Full
IV
2.0
ns
tHSRF
SDFS to SCLK
u Hold Time
Full
IV
4.0
ns
tSSF
SDFS to SCLK
t Setup Time
5
Full
IV
1.0
ns
tHSF
SDFS to SCLK
t Hold Time
5
Full
IV
2.0
ns
Serial Frame Output Timing:
tDSE
SCLK
u to SDFE Delay Time
Full
IV
3.5
11.0
ns
tSDFEH
SDFE Width High
Full
V
tSCLK
ns
tDSO
SCLK
u to SDO Delay Time
Full
IV
4.5
11.0
ns
SCLK Switching Characteristics, SBM = “1”:
tSCLK
SCLK Period4
Full
I
2
× t
CLK
ns
tSCLKL
SCLK Width Low
Full
V
0.5
× tSCLK
ns
tSCLKH
SCLK Width High
Full
V
0.5
× tSCLK
ns
tSCLKD
CLK to SCLK Delay Time
Full
V
6.5
13.0
ns
Serial Frame Timing, SBM = “1”:
tDSF
SCLK
u to SDFS Delay Time
Full
IV
1.0
4.0
ns
tSDFSH
SDFS Width High
Full
V
tSCLK
ns
SCLK Timing Requirements, SBM = “0”:
tSCLK
SCLK Period
Full
I
15.4
ns
tSCLKL
SCLK Width Low
Full
IV
0.4
× tSCLK
0.5
× tSCLK
ns
tSCLKH
SCLK Width High
Full
IV
0.4
× t
SCLK
0.5
× t
SCLK
ns
NOTES
1This specification valid for VDD >= 3.3 V. t
CLKL and tCLKH still apply.
2Specification pertains to: IN[15:0], EXP[2:0], A/B.
3Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
4SCLK period will be
≥ 2 × t
CLK when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
5SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
Specifications subject to change without notice.
相關(guān)PDF資料
PDF描述
AD6623ASZ IC TSP 4CHAN 104MSPS 128MQFP
AD6641BCPZRL7-500 IC IF RCVR 11BIT 200MSPS 56LFCSP
AD664BJ IC DAC 12BIT QUAD MONO 44-JLCC
AD667BD IC DAC 12BIT W/BUFF LTCH 28-CDIP
AD669BN IC DAC 16BIT MONO VREF 28-DIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD6620ASZ-REEL 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD6620PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
AD6620S 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor
AD6620S/PCB 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk
AD6622 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*