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參數(shù)資料
| 型號： | AD6620ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接口： | 并行/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-BQFP |
| 供應(yīng)商設(shè)備封裝： | 80-PQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
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AD6620
–23–
REV. A
The frequency response of the filter is given by the following
equations. The gain and pass band droop of CIC5 should be
calculated by these equations. Both parameters may be compen-
sated for in the RCF stage.
Hz
z
S
M
CIC
()
–
=×
+
1
2
1
5
51
5
Hf
Mf
f
S
CIC
SAMP
CIC
()
sin
=×
×
+
1
2
5 5
5
2
5
π
The scale factor, SCIC5 is a programmable unsigned integer
between 0 and 20. It serves to control the attenuation of the
data into the CIC5 stage in 6 dB increments. For the best dynamic
range, SCIC5 should be set to the smallest value possible (lowest
attenuation) without creating an overflow condition. This can
be safely accomplished using the equation below, where OLCIC2
is the largest fraction of full scale possible at the input to this
filter stage. This value is output from the CIC2 stage then pipe-
lined into the CIC5. SCIC5 is ignored when this filter is bypassed
by setting MCIC5 = 1.
S
ceil
M
OL
M
OL
CIC
S
CIC
52
5
2
5
2
5
2
5
=×
()
= () ×
+
log (
) –
when CIC5 is bypassed;
OL
CIC
52
=
The output rate of this stage is given by the equation below.
f
M
SAMP
CIC
5
2
5
≤
–0.5
–120
–100
–80
–60
–40
–20
0
dBFS
f/fSAMP
–0.4 –0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
–0.5
–120
–100
–80
–60
–40
–20
0
dBFS
f/fSAMP2
–0.4 –0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0
Figure 37. CIC2 Alias Rejection, MCIC2 = 16
5TH ORDER CASCADED INTEGRATOR COMB FILTER
The third signal processing stage, CIC5, implements a sharper
fixed-coefficient, decimating filter than CIC2. The input rate to
this filter is fSAMP2. The maximum input rate is given by the
equation below. NCH equals two for Diversity Channel Real
input mode; otherwise NCH equals one. In order to satisfy this
equation, MCIC2 can be increased, NCH can be reduced, or fCLK
can be increased (reference fractional rate input timing described
in the Input Timing section).
f
N
SAMP
CLK
CH
2
≤
×
The decimation ratio, MCIC5, may be programmed from 1 to 32
(all integer values). When MCIC5 = 1, this stage is bypassed and
the CIC5 scale factor is ignored.
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| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
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