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參數(shù)資料
| 型號： | AD6620ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 接口： | 并行/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-BQFP |
| 供應(yīng)商設(shè)備封裝： | 80-PQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
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AD6620
–28–
REV. A
Table IX. Control Register and RAM Addresses
Address
Bit Width
Name
Notation
Description
000–0FF
20
RCF Coefficient RAM
100–1FF
36
RCF Data RAM
200–27F
0
Reserved
300
8
MODE CONTROL REGISTER
0: SOFT_RESET
1
1: Diversity Channel Real Input Mode
2: Single Channel Complex Input Mode
3: Sync Master/Slave
2 (Master = 1,
Slave = 0)
7–4: Reserved
301
3
NCO CONTROL REGISTER
0: NCO Bypass (Bypass = 1, Active = 0)
1: Enable Phase Dither
2: Enable Amplitude Dither
7–3: Reserved
302
32
NCO SYNC CONTROL REGISTER
SYNC_MASK
Write: Sync Mask Shadow
Read: Sync Mask
303
32
NCO_FREQ
Channel Frequency for NCO Tuning
304
16
NCO PHASE_OFFSET
NCO Phase Offset
305
8
INPUT/CIC2 SCALE REGISTER
2–0: SCIC2
3: Reserved
4: ExpInv
7–5: : ExpOff
306
8
MCIC2 – 1MCIC2 – 1
CIC2 Decimation Minus One
307
5
CIC5 SCALE REGISTER
SCIC5
4–0: SCIC5
7–5: Reserved
308
8
MCIC5 – 1MCIC5 – 1
CIC5 Decimation Minus One
309
4
OUTPUT/RCF CONTROL REGISTER
SOUT
2–0: Output Scale Factor
3: Unique B Flag (Normal Mode = 0,
Unique B Mode = 1)
7–4: Reserved
30A
8
MRCF – 1MRCF – 1
RCF Decimation Minus One
30B
8
RCF ADDRESS OFFSET REGISTER
RCFOFF
Filter Coefficient Address Offset
30C
8
NTAPS – 1NTAPS – 1
Number of Taps Minus One
30D
8
Reserved (Should Be Written 0)
NOTES
1This bit is set high on
RESET. The chip is held into SOFT_RESET until it is written low.
2This bit is set low on
RESET. This keeps multiple AD6620 SYNC Masters from driving each other.
outputs while acting as a sync master, or as inputs while acting
as a sync slave. This is the only register with a defined power-up
state: on power-up, Bit 0 will be at a Logic “1.” This places the
chip in SOFT_RESET and defines the chip as a sync slave.
Powering up as a sync slave avoids contention problems when
connecting multiple AD6620s.
If Bit 0 is written low and Bits 2 and 1 are low, the AD6620 is in
Single Channel Real Mode. If Bit 1 is high and Bits 0 and 2 are
low, the device is in the Diversity Channel Real Mode. If Bit 2
is high and Bits 0 and 1 are low, the chip is in the Single Chan-
nel Complex Mode. Setting Bit 3 high configures the AD6620
as a SYNC master; the SYNC pins are then used as outputs. If
Bit 3 is low, it is a SYNC slave and the SYNC pins function
as inputs. Bits 7–4 are reserved and should be written low.
(0x301) NCO Control Register
This register allows control of special features of the NCO. If
Bit 0 of this register is high the NCO of the AD6620 is by-passed.
Both the I data and the Q data that are passed through the chip
will be the same and the Spectrum will not be translated. In
bypass the input data is attenuated by 12 dB.
(0x000–0xFF) RCF Coefficient RAM
Memory that stores user-programmable coefficients for the RCF
filter. The RAM will hold 256 20-bit twos complement words
for a maximum filter length of 256 taps. In Diversity Channel
Real Mode the filter length is limited to 128 taps per channel.
The number of taps used is controlled by NTAPS–1 (30C) regard-
less of the number of coefficient locations programmed. If filter
size allows, more than one filter can be resident in the memory
at a time. This makes it possible to switch filters without reloading
all of the coefficients.
(0x100–0x1FF) RCF Data RAM
These locations store I and Q data exiting the CIC5 filter stage
while the RCF performs multiply accumulates. The lower 18
bits of the 36-bit location is I data; the upper 18 bits are Q data.
These locations are addressed in memory and are available via
the control ports so that the data RAM can be flushed for test-
ing and simulation purposes. They are not cleared on reset.
(0x300) Mode Control Register
This location brings the chip out of reset and sets the operating
mode. It also specifies how the chip will use its SYNC pins: as
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| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
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