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參數(shù)資料
| 型號： | AD6620ASZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/44頁 |
| 文件大小： | 0K |
| 描述： | IC DGTL RCVR DUAL 67MSPS 80-PQFP |
| 標準包裝： | 1 |
| 接口： | 并行/串行 |
| 電源電壓： | 3 V ~ 3.6 V |
| 封裝/外殼： | 80-BQFP |
| 供應商設(shè)備封裝： | 80-PQFP（14x14） |
| 包裝： | 托盤 |
| 安裝類型： | 表面貼裝 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
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AD6620
–3–
REV. A
Following CIC2 is the second fixed-coefficient decimating filter.
This filter, CIC5, further reduces the sample rate by a program-
mable ratio from 1 to 32. The data rate out of CIC5, fSAMP5, is
determined by the decimation factors of MCIC5 and MCIC2.
Each CIC stage is a FIR filter whose response is defined by the
decimation rate. The purpose of these filters is to reduce the
data rate of the incoming signal so that the final filter stage, a FIR
RAM coefficient sum-of-products filter (RCF), can calculate
more taps per output. As shown in Figure 1, on-chip multiplex-
ers allow both CIC filters to be bypassed if a multirate clock
is used.
The fourth stage is a sum-of-products FIR filter with program-
mable 20-bit coefficients, and decimation rates programmable
from 1 to 32. The RAM Coefficient FIR Filter (RCF in Figure
1) can handle a maximum of 256 taps.
The overall filter response for the AD6620 is the composite of
all three cascaded decimating filters: CIC2, CIC5, and RCF. Each
successive filter stage is capable of narrower transition band-
widths but requires a greater number of CLK cycles to calculate
the output. More decimation in the first filter stage will minimize
overall power consumption. Data comes out via a parallel port
or a serial interface.
Figure 2 illustrates the basic function of the AD6620: to select
and filter a single channel from a wide input spectrum. The
frequency translator “tunes” the desired carrier to baseband.
CIC2 and CIC5 have fixed order responses; the RCF filter
provides the sharp transitions. More detail is provided in later
sections of the data sheet.
–fS/2
–3fS/8
–5fS/16
–fS/4
–3fS/16
–fS/8
–fS/16
DC
fS/16
fS/8
3fS/16
fS/4
5fS/16
fS/2
3fS/8
SIGNAL OF
INTEREST
SIGNAL OF INTEREST "IMAGE"
WIDEBAND INPUT SPECTRUM
(–fsamp/2 TO fsamp/2)
D'
C'
B'
A'
A
C
B
D
Figure 2a. Wideband Input Spectrum (e.g., 30 MHz from High-Speed ADC)
–fS/2
–3fS/8
–5fS/16
–fS/4
–3fS/16
–fS/8
–fS /16
DC
fS/16
fS/8
3fS/16
fS/4
5fS/16
fS/2
3fS/8
AFTER FREQUENCY TRANSLATION
NCO "TUNES" SIGNAL TO BASEBAND
A
B
C
D
D'
C'
B'
A'
Figure 2b. Frequency Translation (e.g., Single 1 MHz Channel Tuned to Baseband)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
CIC2, CIC5, AND RCF
dBc
FREQUENCY
Figure 2c. Baseband Signal is Decimated and Filtered by CIC2, CIC5, RCF
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| AD6620ASZ-REEL | 功能描述:IC DGTL RCVR DUAL 67MSPS 80-PQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD6620PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S | 制造商:AD 制造商全稱:Analog Devices 功能描述:65 MSPS Digital Receive Signal Processor |
| AD6620S/PCB | 制造商:Analog Devices 功能描述:DUAL CHANNEL DECIMATING RECEIV 制造商:Analog Devices 功能描述:SGNL PROCESSOR 169CSPBGA - Bulk |
| AD6622 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Four-Channel, 75 MSPS Digital Transmit Signal Processor TSP |
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