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參數(shù)資料
型號: AD5757ACPZ
廠商: Analog Devices Inc
文件頁數(shù): 40/44頁
文件大?。?/td> 0K
描述: IC DAC 16BIT QUAD 64-LFCSP
特色產(chǎn)品: AD5755 / AD5755-1 / AD5757 DACs
標(biāo)準(zhǔn)包裝: 1
設(shè)置時間: 15µs
位數(shù): 16
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 4
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 64-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 64-LFCSP-VQ(9x9)
包裝: 管件
輸出數(shù)目和類型: *
采樣率(每秒): *
Data Sheet
AD5757
Rev. D | Page 5 of 44
SPECIFICATIONS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 ; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
CURRENT OUTPUT
Output Current Ranges
0
24
mA
0
20
mA
4
20
mA
Resolution
16
Bits
ACCURACY (EXTERNAL RSET)
Assumes ideal resistor; see the External Current
Setting Resistor section for more information
Total Unadjusted Error (TUE)
0.05
±0.009
+0.05
% FSR
TUE Long-Term Stability
100
ppm FSR
Drift after 1000 hours, TJ = 150°C
Relative Accuracy (INL)
0.006
+0.006
% FSR
Differential Nonlinearity (DNL)
1
+1
LSB
Guaranteed monotonic
Offset Error
0.05
±0.005
+0.05
% FSR
Offset Error Drift2
±4
ppm FSR/°C
Gain Error
0.05
±0.004
+0.05
% FSR
Gain TC2
±3
ppm FSR/°C
Full-Scale Error
0.05
±0.008
+0.05
% FSR
Full-Scale TC2
±5
ppm FSR/°C
DC Crosstalk
0.0005
% FSR
External RSET
ACCURACY (INTERNAL RSET)
Total Unadjusted Error (TUE)3, 4
0.14
+0.14
% FSR
0.11
±0.009
+0.11
% FSR
TA = 25°C
TUE Long-Term Stability
180
ppm FSR
Drift after 1000 hours, TJ = 150°C
Relative Accuracy (INL)
0.006
+0.006
% FSR
0.004
+0.004
% FSR
TA = 25°C
Differential Nonlinearity (DNL)
1
+1
LSB
Guaranteed monotonic
Offset Error3, 4
0.05
+0.05
% FSR
0.04
±0.007
+0.04
% FSR
TA = 25°C
Offset Error Drift2
±6
ppm FSR/°C
Gain Error
0.12
+0.12
% FSR
0.06
±0.002
+0.06
% FSR
TA = 25°C
Gain TC2
±9
ppm FSR/°C
Full-Scale Error3, 4
0.14
+0.14
% FSR
0.1
±0.007
+0.1
% FSR
TA = 25°C
Full-Scale TC2
±14
ppm FSR/°C
DC Crosstalk4
0.011
% FSR
Internal RSET
OUTPUT CHARACTERISTICS2
Current Loop Compliance Voltage
VBOOST_x
2.4
VBOOST_x
2.7
V
Output Current Drift vs. Time
Drift after 1000 hours, scale output, TJ = 150°C
90
ppm FSR
External RSET
140
ppm FSR
Internal RSET
Resistive Load
1000
The dc-to-dc converter has been characterized
with a maximum load of 1 k, chosen such that
compliance is not exceeded; see Figure 31 and
DC-DC MaxV bits in Table 24
Output Impedance
100
M
DC PSRR
0.02
1
A/V
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
4.95
5
5.05
V
For specified performance
DC Input Impedance
45
150
M
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