參數(shù)資料
型號(hào)： AD5757ACPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 32/44頁(yè)
文件大小： 0K
描述： IC DAC 16BIT QUAD 64-LFCSP
特色產(chǎn)品： AD5755 / AD5755-1 / AD5757 DACs
標(biāo)準(zhǔn)包裝： 1
設(shè)置時(shí)間： 15µs
位數(shù)： 16
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 4
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 管件
輸出數(shù)目和類型： *
采樣率（每秒）： *
AD5757
Data Sheet
Rev. D | Page 38 of 44
DC-to-DC Converter Compensation Capacitors
As the dc-to-dc converter operates in DCM, the uncompensated
transfer function is essentially a single-pole transfer function.
The pole frequency of the transfer function is determined by
the dc-to-dc converter’s output capacitance, input and output
voltage, and output load. The AD5757 uses an external capaci-
tor in conjunction with an internal 150 k resistor to compensate
the regulator loop. Alternatively, an external compensation
resistor can be used in series with the compensation capacitor
by setting the DC-DC Comp bit in the dc-to-dc control register.
In this case, a ~50 k resistor is recommended. A description
of the advantages of this can be found in the AICC Supply
Requirements—Slewing section. For typical applications, a
10 nF dc-to-dc compensation capacitor is recommended.
DC-to-DC Converter Input and Output Capacitor
Selection
The output capacitor affects ripple voltage of the dc-to-dc con-
verter and indirectly limits the maximum slew rate at which the
channel output current can rise. The ripple voltage is caused by
a combination of the capacitance and equivalent series resistance
(ESR) of the capacitor. For the AD5757, a ceramic capacitor
of 4.7 F is recommended for typical applications. Larger
capacitors or paralleled capacitors improve the ripple at the
expense of reduced slew rate. Larger capacitors also impact
the AVCC supplies current requirements while slewing (see the
AICC Supply Requirements—Slewing section). This capacitance
at the output of the dc-to-dc converter should be >3 F under
all operating conditions.
The input capacitor provides much of the dynamic current
required for the dc-to-dc converter and should be a low ESR
component. For the AD5757, a low ESR tantalum or ceramic
capacitor of 10 F is recommended for typical applications.
Ceramic capacitors must be chosen carefully because they can
exhibit a large sensitivity to dc bias voltages and temperature.
X5R or X7R dielectrics are preferred because these capacitors
remain stable over wider operating voltage and temperature
ranges. Care must be taken if selecting a tantalum capacitor to
ensure a low ESR value.
AICC SUPPLY REQUIREMENTS—STATIC
The dc-to-dc converter is designed to supply a VBOOST_x voltage of
VBOOST = IOUT × RLOAD + Headroom
(2)
See Figure 31 for a plot of headroom supplied vs. output
voltage. This means that, for a fixed load and output voltage,
the dc-to-dc converter output current can be calculated by
the following formula:
CC
V
BOOST
OUT
CC
AV
V
I
AV
Efficiency
Out
Power
AI
BOOST
×
=
×
=
η
(3)
where:
IOUT is the output current from IOUT_x in amps.
ηV
BOOST
is the efficiency at VBOOST_x as a fraction (see Figure 33
AICC SUPPLY REQUIREMENTS—SLEWING
The AICC current requirement while slewing is greater than in
static operation because the output power increases to charge
the output capacitance of the dc-to-dc converter. This transient
current can be quite large (see Figure 58), although the methods
can reduce the requirements on the AVCC supply. If not enough
AICC current can be provided, the AVCC voltage drops. Due to
this AVCCdrop, the AICC current required to slew increases
further. This means that the voltage at AVCC drops further (see
Equation 3) and the VBOOST_x voltage, and thus the output volt-
age, may never reach its intended value. Because this AVCC
voltage is common to all channels, this may also affect other
channels.
0
5
10
15
20
25
30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0
0.5
1.0
1.5
2.0
2.5
I O
UT
_
x
CURRE
NT
(
mA
)/
V
B
OOS
T
_
x
VO
LT
A
G
E
(V)
AI
CC
CURRE
NT
(
A)
TIME (ms)
AICC
IOUT
VBOOST
0mA TO 24mA RANGE
1k LOAD
fSW = 410kHz
INDUCTOR = 10H (XAL4040-103)
TA = 25°C
09225-
184
Figure 58. AICC Current vs. Time for 24 mA Step Through 1 k Load
with Internal Compensation Resistor
Reducing AICC Current Requirements
There are two main methods that can be used to reduce the
AICC current requirements. One method is to add an external
compensation resistor, and the other is to use slew rate control.
Both of these methods can be used in conjunction.
A compensation resistor can be placed at the COMPDCDC_x pin
in series with the 10 nF compensation capacitor. A 51 k external
compensation resistor is recommended. This compensation
increases the slew time of the current output but eases the AICC
transient current requirements. Figure 59 shows a plot of AICC
current for a 24 mA step through a 1 k load when using a
51 k compensation resistor. This method eases the current
requirements through smaller loads even further, as shown in
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