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參數(shù)資料
| 型號(hào)： | AD5757ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/44頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 16BIT QUAD 64-LFCSP |
| 特色產(chǎn)品： | AD5755 / AD5755-1 / AD5757 DACs |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 設(shè)置時(shí)間： | 15µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 4 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | * |
| 采樣率（每秒）： | * |
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AD5757
Data Sheet
Rev. D | Page 26 of 44
PROGRAMMING SEQUENCE TO WRITE/ENABLE
THE OUTPUT CORRECTLY
To correctly write to and set up the part from a power-on
condition, use the following sequence:
1. Perform a hardware or software reset after initial power-on.
2. The dc-to-dc converter supply block must be configured.
Set the dc-to-dc switching frequency, maximum output
voltage allowed, and the phase that the four dc-to-dc
channels clock at.
3. Configure the DAC control register on a per channel basis.
The output range is selected, and the dc-to-dc converter
block is enabled (DC_DC bit). Other control bits can be
configured at this point. Set the INT_ENABLE bit;
however, the output enable bit (OUTEN) should not be set.
4. Write the required code to the DAC data register. This
implements a full DAC calibration internally. Allow at least
200 s before Step 5 for reduced output glitch.
5. Write to the DAC control register again to enable the
output (set the OUTEN bit).
A flowchart of this sequence is shown in Figure 51.
POWER ON.
STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.
STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS.
ALLOW AT LEAST 200s BETWEEN STEP 3
AND STEP 5 FOR REDUCED OUTPUT GLITCH.
STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO
SET DC-TO-DC CLOCK FREQUENCY, PHASE,
AND MAXIMUM VOLTAGE.
STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT
THE DAC CHANNEL AND OUTPUT RANGE.
SET THE DC_DC BIT AND OTHER CONTROL
BITS AS REQUIRED. SET THE INT_ENABLE BIT
BUT DO NOT SELECT THE OUTEN BIT.
STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD
SEQUENCE AS IN STEP 3 ABOVE. THIS TIME
SELECT THE OUTEN BIT TO ENABLE
THE OUTPUT.
09225-
073
Figure 51. Programming Sequence for Enabling the Output Correctly
CHANGING AND REPROGRAMMING THE RANGE
When changing between ranges, the same sequence as
described in the Programming Sequence to Write/Enable the
Output Correctly section should be used. It is recommended to
set the range to zero scale prior to disabling the output. Because
the dc-to-dc switching frequency, maximum voltage, and phase
have already been selected, there is no need to reprogram these.
A flowchart of this sequence is shown in Figure 52.
CHANNEL’S OUTPUT IS ENABLED.
STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.
STEP 1: WRITE TO CHANNEL’S DAC DATA
REGISTER. SET THE OUTPUT
TO 0V (ZERO OR MIDSCALE).
STEP 2: WRITE TO DAC CONTROL REGISTER.
DISABLE THE OUTPUT (OUTEN = 0), AND
SET THE NEW OUTPUT RANGE. KEEP THE
DC_DC BIT AND THE INT_ENABLE BIT SET.
STEP 4: WRITE TO DAC CONTROL REGISTER.
RELOAD SEQUENCE AS IN STEP 2 ABOVE.
THIS TIME SELECT THE OUTEN BIT TO
ENABLE THE OUTPUT.
09225-
074
Figure 52. Steps for Changing the Output Range
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| AD5757ACPZ-REEL7 | 功能描述:IC DAC 16BIT QUAD IOUT 64LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
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