參數(shù)資料
型號： AD5757ACPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： SERIAL INPUT LOADING, 15 us SETTLING TIME, 16-BIT DAC, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁數(shù)： 41/44頁
文件大?。?/td> 1122K
代理商： AD5757ACPZ-REEL7
AD5757
Rev. A | Page 6 of 44
AC PERFORMANCE CHARACTERISTICS
AVDD = VBOOST_x = 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Current Output
Output Current Settling Time
15
μs
To 0.1% FSR (0 mA to 24 mA)
See test conditions/
comments
ms
Output Noise (0.1 Hz to 10 Hz
Bandwidth)
0.15
LSB p-p
16-bit LSB, 0 mA to 24 mA range
Output Noise Spectral Density
0.5
nA/√Hz
Measured at 10 kHz, midscale output, 0
mA to 24 mA range
1 Guaranteed by design and characterization; not production tested.
TIMING CHARACTERISTICS
AVDD = VBOOST_x= 15 V; DVDD = 2.7 V to 5.5 V; AVCC = 4.5 V to 5.5 V; dc-to-dc converter disabled; AGND = DGND = GNDSWx = 0 V;
REFIN = 5 V; RL = 300 Ω; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
13
ns min
SCLK low time
t4
13
ns min
SYNC falling edge to SCLK falling edge setup time
t5
13
ns min
24th/32nd SCLK falling edge to SYNC rising edge (see
t6
198
ns min
SYNC high time
t7
5
ns min
Data setup time
t8
5
ns min
Data hold time
t9
20
μs min
SYNC rising edge to LDAC falling edge (all DACs updated or any channel has
digital slew rate control enabled)
5
μs min
SYNC rising edge to LDAC falling edge (single DAC updated)
t10
10
ns min
LDAC pulse width low
t11
500
ns max
LDAC falling edge to DAC output response time
t12
μs max
DAC output settling time
t13
10
ns min
CLEAR high time
t14
5
μs max
CLEAR activation time
t15
40
ns max
SCLK rising edge to SDO valid
t16
21
μs min
SYNC rising edge to DAC output response time (LDAC = 0) (all DACs updated)
5
μs min
SYNC rising edge to DAC output response time (LDAC = 0) (single DAC updated)
t17
500
ns min
LDAC falling edge to SYNC rising edge
t18
800
ns min
RESET pulse width
20
μs min
SYNC high to next SYNC low (digital slew rate control enabled) (all DACs updated)
5
μs min
SYNC high to next SYNC low (digital slew rate control disabled) (single DAC
updated)
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tRISE = tFALL = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.
4 This specification applies if LDAC is held low during the write cycle; otherwise, see t9.
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