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| 型號： | AD5757ACPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 15 us SETTLING TIME, 16-BIT DAC, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 21/44頁 |
| 文件大?。?/td> | 1122K |
| 代理商： | AD5757ACPZ-REEL7 |
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AD5757
Rev. A | Page 28 of 44
CONTROL REGISTERS
When writing to a control register, the format shown in Table 15
must be used. See Table 8 for information on the configuration
of Bit D23 to Bit D16. The control registers are addressed by setting
the DREG[2:0] bits to 111 and then setting the CREG[2:0] bits
to the appropriate decode address for that register, according to
Table 16. These CREG bits select among the various control
registers.
Main Control Register
The main control register options are shown in Table 17 and
Table 18. See the Device Features section for more information
on the features controlled by the main Control Register.
Table 15. Writing to a Control Register
MSB
LSB
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12 to D0
R/W
DUT_AD1
DUT_AD0
1
DAC_AD1
DAC_AD0
CREG2
CREG1
CREG0
Data
Table 16. Register Access Decode
CREG2 (D15)
CREG1 (D14)
CREG0 (D13)
Function
0
Slew rate control register (one per channel)
0
1
Main control register
0
1
0
DAC control register (one per channel)
0
1
DC-to-dc control register
1
0
Software register (one per channel)
Table 17. Programming the Main Control Register
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3 to D0
0
1
0
STATREAD
EWD
WD1
WD0
X1
OUTEN_ALL
DCDC_ALL
X1
1 X = don’t care.
Table 18. Main Control Register Functions
Bit
Description
STATREAD
Enable status readback during a write. See the Device Features section.
STATREAD = 1, enable.
STATREAD = 0, disable (default).
EWD
Enable watchdog timer. See the Device Features section for more information.
EWD = 1, enable watchdog.
EWD = 0, disable watchdog (default).
WD1, WD0
Timeout select bits. Used to select the timeout period for the watchdog timer.
WD1
WD0
Timeout Period (ms)
0
5
0
1
10
1
0
100
1
200
OUTEN_ALL
Enables the output on all four DACs simultaneously.
Do not use the OUTEN_ALL bit when using the OUTEN bit in the DAC control register.
DCDC_ALL
When set, powers up the dc-to-dc converter on all four channels simultaneously.
To power down the dc-to-dc converters, all channel outputs must first be disabled.
Do not use the DCDC_ALL bit when using the DC_DC bit in the DAC control register.
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