參數(shù)資料
型號(hào)： AD5757ACPZ-REEL7
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： DAC
英文描述： SERIAL INPUT LOADING, 15 us SETTLING TIME, 16-BIT DAC, QCC64
封裝： 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
文件頁(yè)數(shù)： 18/44頁(yè)
文件大?。?/td> 1122K
代理商： AD5757ACPZ-REEL7
AD5757
Rev. A | Page 25 of 44
PROGRAMMING SEQUENCE TO WRITE/ENABLE
THE OUTPUT CORRECTLY
To correctly write to and set up the part from a power-on
condition, use the following sequence:
1.
Perform a hardware or software reset after initial power-on.
2.
The dc-to-dc converter supply block must be configured.
Set the dc-to-dc switching frequency, maximum output
voltage allowed, and the phase that the four dc-to-dc
channels clock at.
3.
Configure the DAC control register on a per channel basis.
The output range is selected, and the dc-to-dc converter
block is enabled (DC_DC bit). Other control bits can be
configured at this point. Set the INT_ENABLE bit;
however, the output enable bit (OUTEN) should not be set.
4.
Write the required code to the DAC data register. This
implements a full DAC calibration internally. Allow at least
200 μs before Step 5 for reduced output glitch.
5.
Write to the DAC control register again to enable the
output (set the OUTEN bit).
A flowchart of this sequence is shown in Figure 51.
POWER ON.
STEP 1: PERFORM A SOFTWARE/HARDWARE RESET.
STEP 4: WRITE TO EACH/ALL DAC DATA REGISTERS.
ALLOW AT LEAST 200s BETWEEN STEP 3
AND STEP 5 FOR REDUCED OUTPUT GLITCH.
STEP 2: WRITE TO DC-TO-DC CONTROL REGISTER TO
SET DC-TO-DC CLOCK FREQUENCY, PHASE,
AND MAXIMUM VOLTAGE.
STEP 3: WRITE TO DAC CONTROL REGISTER. SELECT
THE DAC CHANNEL AND OUTPUT RANGE.
SET THE DC_DC BIT AND OTHER CONTROL
BITS AS REQUIRED. SET THE INT_ENABLE BIT
BUT DO NOT SELECT THE OUTEN BIT.
STEP 5: WRITE TO DAC CONTROL REGISTER. RELOAD
SEQUENCE AS IN STEP 3 ABOVE. THIS TIME
SELECT THE OUTEN BIT TO ENABLE
THE OUTPUT.
0922
5-
073
Figure 51. Programming Sequence for Enabling the Output Correctly
CHANGING AND REPROGRAMMING THE RANGE
When changing between ranges, the same sequence as
Output Correctly section should be used. It is recommended to
set the range to zero scale prior to disabling the output. Because
the dc-to-dc switching frequency, maximum voltage, and phase
have already been selected, there is no need to reprogram these.
A flowchart of this sequence is shown in Figure 52.
CHANNEL’S OUTPUT IS ENABLED.
STEP 3: WRITE VALUE TO THE DAC DATA REGISTER.
STEP 1: WRITE TO CHANNEL’S DAC DATA
REGISTER. SET THE OUTPUT
TO 0V (ZERO OR MIDSCALE).
STEP 2: WRITE TO DAC CONTROL REGISTER.
DISABLE THE OUTPUT (OUTEN = 0), AND
SET THE NEW OUTPUT RANGE. KEEP THE
DC_DC BIT AND THE INT_ENABLE BIT SET.
STEP 4: WRITE TO DAC CONTROL REGISTER.
RELOAD SEQUENCE AS IN STEP 2 ABOVE.
THIS TIME SELECT THE OUTEN BIT TO
ENABLE THE OUTPUT.
0
922
5-
0
74
Figure 52. Steps for Changing the Output Range
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