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參數(shù)資料
| 型號(hào)： | AD5757ACPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 15 us SETTLING TIME, 16-BIT DAC, QCC64 |
| 封裝： | 9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 1122K |
| 代理商： | AD5757ACPZ-REEL7 |
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AD5757
Rev. A | Page 39 of 44
APPLICATIONS INFORMATION
CURRENT OUTPUT MODE WITH INTERNAL RSET
When using the internal RSET resistor in current output mode,
the output is significantly affected by how many other channels
using the internal RSET are enabled and by the dc crosstalk from
for all channels enabled with the internal RSET selected and
outputting the same code.
For every channel enabled with the internal RSET, the offset error
decreases. For example, with one current output enabled using
the internal RSET, the offset error is 0.075% FSR. This value
decreases proportionally as more current channels are enabled;
the offset error is 0.056% FSR on each of two channels, 0.029%
on each of three channels, and 0.01% on each of four channels.
Similarly, the dc crosstalk when using the internal RSET is propor-
tional to the number of current output channels enabled with
the internal RSET. For example, with the measured channel at
0x8000 and one channel going from zero to full scale, the dc
crosstalk is 0.011% FSR. With two channels going from zero to
full scale, it is 0.019% FSR, and with all three other channels
going from zero to full scale, it is 0.025% FSR.
For the full-scale error measurement in Table 1, all channels are
at 0xFFFF. This means that, as any channel goes to zero scale,
the full-scale error increases due to the dc crosstalk. For example,
with the measured channel at 0xFFFF and three channels at
zero scale, the full-scale error is 0.025%. Similarly, if only one
channel is enabled in current output mode with the internal
RSET, the full-scale error is 0.025% FSR + 0.075% FSR = 0.1% FSR.
PRECISION VOLTAGE REFERENCE SELECTION
To achieve the optimum performance from the AD5757 over its
full operating temperature range, a precision voltage reference
must be used. Thought should be given to the selection of a
precision voltage reference. The voltage applied to the reference
inputs is used to provide a buffered reference for the DAC cores.
Therefore, any error in the voltage reference is reflected in the
outputs of the device.
There are four possible sources of error to consider when choosing
a voltage reference for high accuracy applications: initial
accuracy, temperature coefficient of the output voltage, long-
term drift, and output voltage noise.
Initial accuracy error on the output voltage of an external refer-
ence can lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can be used at any temperature to trim out any error.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference’s output voltage affects
INL, DNL, and TUE. A reference with a tight temperature
coefficient specification should be chosen to reduce the depend-
ence of the DAC output voltage to ambient temperature.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered.
Choosing a reference with as low an output noise voltage as practi-
cal for the system resolution required is important. Precision
voltage references such as the ADR435 (XFET design) produce
low output noise in the 0.1 Hz to 10 Hz region. However, as the
circuit bandwidth increases, filtering the output of the reference
may be required to minimize the output noise.
DRIVING INDUCTIVE LOADS
When driving inductive or poorly defined loads, a capacitor
may be required between IOUT_x and AGND to ensure stability. A
0.01 μF capacitor between IOUT_x and AGND ensures stability of
a load of 50 mH. The capacitive component of the load may
cause slower settling, although this may be masked by the set-
tling time of the AD5757. There is no maximum capacitance
limit for the current output of the AD5757.
Table 34. Recommended Precision References
Part No.
Initial Accuracy
(mV Maximum)
Long-Term Drift
(ppm Typical)
Temperature Drift (ppm/°C Maximum)
0.1 Hz to 10 Hz Noise
(μV p-p Typical)
±2
50
3
2.25
±3
50
3
10
40
3
8
±5
50
9
8
±2.5
15
10
4
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