- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1978 > ACS8947T (Semtech)IC JITTER ATT MULT PLL 48-QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 30/30頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁當(dāng)前第30頁
ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 9
www.semtech.com
The ACS8947T is available in a small form factor QFN48
package of outer dimensions 7 mm x 7 mm x 0.9 mm.
Figure 3 Example of EVB GUI
An evaluation board and GUI software for calculating the
required loop filter component values and configuration
wiring connections, and for hands-on device assessment,
are available on request.
Inputs
Clock Inputs
The ACS8947T has two LVPECL differential clock inputs
(CLK1N/P and CLK2N/P) and is capable of locking across
a wide frequency range of 580 kHz to 180 MHz. If both
input clocks are being used, the frequency difference
between the signals presented to CLK1N/P and CLK2N/P
must be within ±100 ppm. Unused positive differential
inputs should be wired to GND and unused negative
differential inputs should be wired to VDD.
The clock inputs are designed to accept LVDS, LVPECLor
CML inputs, given suitable passive resistive and
capacitive interface components.
On device reset, the configuration protocol presets the
internal divider ratios and enables a fast frequency tuning
algorithm that temporarily forces PLL bandwidth and
locking range to be wide. This enables the PLL to
automatically scan and lock to the target reference
frequency present on the selected input channel.Once
lock is acquired, the PLL bandwidth is reduced and
frequency tracking range limited to ±200 ppm. It is
therefore important to ensure that the correct input
frequency is present on CLK1N/P and CLK2N/P prior to
resetting the ACS8947T.
See PLL Configuration for details on how to configure the
PLL dividers.
Either clock input can be manually or automatically
selected as the current reference, based on the detection
of clock activity. Signals AUTO_SEL and SEL_CLK2 shown
in Table 5 are used to control the input clock selection. In
automatic mode, the selection between CLK1 and CLK2
is non-revertive: i.e. if the PLL is locked on to CLK1 and
CLK1 fails and the PLL switches to CLK2, when CLK1
becomes operational again, the PLL does not revert to
CLK1.
Table 5 Clock Input Selection Decoding
AUTO_SEL SEL_CLK2
Selected Reference
Feedback Clock
0
CLK1
Internal path
0
1
CLK2
Internal path
1
0
CLK1
CLK2
1
AUTOMATICSELECTION
(determined by
activity monitor)
Internal path
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD10200BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10242BZ | IC ADC DUAL 12BIT 68-CLCC |
| AD10465BZ | IC ADC DUAL 14BIT 68-CLCC |
| AD13280AZ | IC ADC 12BIT 68CLCC |
| AD1377KD | IC ADC SNGL 16BIT 32-CDIP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ACS9010 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Optoelectronic |
| ACS9510/50EVB | 制造商:Semtech Corporation 功能描述: |
| ACS9510EVB | 功能描述:EVALUATION BOARD FOR ACS9510 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:ToPSync™ 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板 |
| ACS9510T | 制造商:Semtech Corporation 功能描述: |
| ACS9520PB | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:ADVANCED COMMS PRODUCT GROUP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。