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參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 20
www.semtech.com
Note: (i) With a 50 ohms load on each pin to VDD -2V
Input and Output Interface Terminations
Interfacing to either the same type or electrically different
interface types is illustrated by the following circuit
diagrams in Figure 13 to Figure 18.
In applications where the output clocks are always
running, they may be AC coupled, allowing the receive end
to be at any common mode voltage, however, the lines
must always be terminated at their characteristic
impedance.
The preferred termination for the CML type output is 50
Ω
to VDD, as shown in Figure 13. AC coupling may be used
subsequently to translate the levels to other interface
types, e.g. to LVPECL/LVDS as shown in Figure 14.
The example of Figure 16 shows LVPECL to LVPECL
terminations with DC coupling, so that the ACS8947T
sees an equivalent load of around 50
Ω from the resistor
arrangement at the receiver end. Note that signal levels
given in the accompanying graph are nominal levels at
622.08 MHz, and will change with load.
The preferred termination circuitry for the LVDS signals
between the ACS8525/26/27 and the ACS8947T
LVPECL is shown in Figure 18. The bias for the LVPECL
input is set for AC inputs at a mid point of approximately
2 V (with VDD of 3.3 V), as opposed to a normal DC
coupled bias of VDD - 2 V. This is due to the push-pull
nature of an AC coupled signal.
Table 14 DC Characteristics: CML Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
IOUT current source
IOUT
13.3
16
19.2
mA
Single-ended output voltage amplitude with 50
Ω
load to VDD and 50 Ω input impedance into next
stage.
VOS
-
400
-
mV
Differential output voltage amplitude with 50
Ω load
to VDD and 50
Ω input impedance into next stage on
both pins.
VOD
-
800
-
mV
Table 15 DC Characteristics: LVPECL Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
LVPECL output low voltage (Note (i))
VOL_LVPECL
VDD-2.1
-
VDD-1.62
V
LVPECL output high voltage (Note (i))
VOH_LVPECL
VDD-1.45
-
VDD-0.88
V
LVPECL output differential voltage (Note (i))
VOD_LVPECL
0.37
-
1.22
V
Table 16 DC Characteristics: LVTTL/CMOS Output Port
Parameter
Symbol
Minimum
Typical
Maximum
Units
Output low voltage @ IOL (MAX)
VOL
--
0.4
V
Output high voltage @ IOH (MIN)
VOH
2.4
-
V
Low level output current @ VOL = 0.4 V
IOL
2-
-
mA
High level output current @ VOH = 2.4 V
IOH
2-
-
mA
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