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Dual Channel, 14-Bit, 65 MSPS A/D Converter
with Analog Input Signal Conditioning
AD10465
Rev. A
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Tel: 781.329.4700
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Fax: 781.461.3113
2006 Analog Devices, Inc. All rights reserved.
FEATURES
The AD10465 uses innovative high density circuit design and laser
trimmed, thin film resistor networks to achieve exceptional
matching and performance, while still maintaining excellent
isolation and providing for significant board area savings.
Dual, 65 MSPS minimum sample rate
Channel-to-channel matching, ±0.5% gain error
Channel-to-channel isolation, >90 dB
DC-coupled signal conditioning included
The AD10465 operates with ±5.0 V supplies for the analog
signal conditioning with a separate 5.0 V supply for the analog-
to-digital conversion and 3.3 V digital supply for the output
stage. Each channel is completely independent, allowing
operation with independent encode and analog inputs. The
AD10465 also offers the user a choice of analog input signal
ranges to further minimize additional external signal
conditioning, while remaining general-purpose.
Selectable bipolar input voltage range
(±0.5 V, ±1.0 V, ±2.0 V)
Gain flatness up to 25 MHz: <0.2 dB
80 dB spurious-free dynamic range
Twos complement output format
3.3 V or 5 V CMOS-compatible output levels
1.75 W per channel
Industrial and military grade
APPLICATIONS
The AD10465 is packaged in a 68-lead ceramic leaded chip
carrier package, footprint-compatible with the earlier
65 MSPS). Manufacturing is done on the Analog Devices Mil-
38534 Qualified Manufacturers Line (QML) and components
are available up to Class-H (40°C to +85°C). The
AD6644internal components are manufactured on Analog Devices’ high
speed complementary bipolar process (XFCB).
Phased array receivers
Communications receivers
FLIR processing
Secure communications
GPS antijamming receivers
Multichannel, multimode receivers
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD10465 is a full channel ADC solution with on-module
signal conditioning for improved dynamic performance and
fully matched channel-to-channel performance. The module
includes two wide dynamic range
AD6644 ADCs. Each
AD6644 has a dc-coupled amplifier front end including an
AD8037 low distortion, high bandwidth amplifier that provides
high input impedance and gain and drives the
AD8138 single-
to-differential amplifier. The
AD6644s have on-chip track-and-
hold circuitry and utilize an innovative multipass architecture
to achieve 14-bit, 65 MSPS performance.
1.
Guaranteed sample rate of 65 MSPS.
2.
Input amplitude options, user configurable.
3.
Input signal conditioning included; both channels matched
for gain.
4.
Fully tested/characterized performance.
5.
Footprint-compatible family; 68-lead CLCC package.
FUNCTIONAL BLOCK DIAGRAM
VREF
DROUT
OUTPUT BUFFERING
TIMING
3
11
14
VREF
DROUT
14
D11 D12A D13A (MSBA) D0B (LSBB) D1B D2B
D3B D4B D5B D6B D7B D8B
OUTPUT BUFFERING
TIMING
9
5
D9B
ENCODEB
DRBOUT
D10B
D11B
D12B
D13B (MSBB)
REF_B
D0A (LSB)
D1A
D2A
D3A
D4A
D5A
D6A
D7A
D8A
D9A
D10A
AD10465
DRAOUT 12
15
16
17
18
19
20
21
22
24
25
23
56
55
52
51
49
48
47
46
45
AINA3
8
AINA2
7
AINA1
6
AINB3
64
REF_A
3
AINB2
63
AINB1
62
28
ENCODEA
29
31
32
33
34
35
36
37
38
39
40
41
42
ENCODEA
0
235
6-
00
1
Figure 1.