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參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 28/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 7
www.semtech.com
35
VCP
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
μA.
36
VCN
A
Analog
Connection for external loop filter components. This is the differential control voltage
input to the internal VCO and the internal differential charge pump output up to a level of
210
μA.
40
RESETB
I
LVTTL/
LVCMOSU
Schmitt
Trigger
Active low reset signal with pull up and Schmitt type input. Used to apply an active-low
Power-on Reset (POR) signal during system initialization. Should be connected via a
capacitor to ground or, if reset control by a microcontroller is required, via a 3.3 V control
line.
41
SYNCP
I
LVPECL
Differential input (typically 8 kHz) where the SYNC signal on this input is sampled and
resynchronized to the rising edge of the OUT1 clock signal. Paired with pin 42 (SYNCN).
Maximum input frequency is 40 MHz. Will accept LVDS, CML or LVPECL signals when
suitable external biasing components are used. See Input and Output Interface
42
SYNCN
I
LVPECL
Differential input (typically 8 kHz) where the SYNC signal on this input is sampled and
resynchronized to the rising edge of the OUT1 clock signal. Paired with pin 41 (SYNCP).
Maximum input frequency is 40 MHz. Will accept LVDS, CML or LVPECL signals when
suitable external biasing components are used. See Input and Output Interface
44
SYNC_OUT
O
LVTTL/
LVCMOS
A sampled and resynchronized version of the SYNC signal present on SYNCP (pin 41) and
SYNCN (pin 42). The SYNC_OUT signal is synchronized to the rising edge of the output
clock present on OUT1. If the SYNC function is used, the output frequency on OUT1
should be at least double the frequency of the SYNCP/SYNCN input and restricted to a
maximum of 80 MHz. This restriction affects the OUT1 signal only.
45
CFG_IN10
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
46
CFG_IN11
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
47
CFG_IN8
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
48
CFG_IN9
I
LVTTL/
LVCMOSD
Configuration input pin. Connection to this pin is defined by the ACS8947T evaluation
software GUI. See PLL Configuration.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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