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參數(shù)資料
| 型號： | ACS8947T |
| 廠商： | Semtech |
| 文件頁數(shù)： | 26/30頁 |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 5
www.semtech.com
5OUT2N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 6. Programmable at
spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the
configuration pin settings at power up or when RESETB is asserted (logic 0).
See PLL Configuration.
The output is ON when VDD02 is supplied with 3.3 V, or OFF when VDD02 is tied to zero
volts. If VDD02 is connected to 0 V, remove the external biasing resistors.
6OUT2P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 5. See OUT2_N (pin 5) for more
detail.
8OUT3N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 9. Programmable at
spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the
configuration pin settings at power up or when RESETB is asserted (logic 0).
See PLL Configuration.
The output is ON when VDD03 is supplied with 3.3 V, or OFF when VDD03 is tied to zero
volts. If VDD03 is connected to 0 V, remove the external biasing resistors.
9OUT3P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 8. See pin 8 description for more
detail.
11
OUT4N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 12. Programmable at
spot frequencies from 1.23 MHz up to 625 MHz. The output frequency is defined by the
configuration pin settings at power up or when RESETB is asserted (logic 0).
See PLL Configuration.
The output is ON when VDD04 is supplied with 3.3 V, or OFF when VDD04 is tied to zero
volts. If VDD04 is connected to 0 V, remove the external biasing resistors.
12
OUT4P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 11. See pin 11 description for more
detail.
13
ALARM1_CO0
O
LVTTL/
LVCMOS
Activity alarm output for the CLK1P/CLK1N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin, that may be connected to CFG_IN[11:0] input pins as
required. See PLL Configuration.
14
ALARM2_CO1
O
LVTTL/
LVCMOS
Activity alarm output for the CLK2P/CLK2N input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up time, where it
is used as a configuration output pin, that may be connected to CFG_IN[11:0] input pins
as required. See PLL Configuration.
15
CFG_OUT2
O
LVTTL/
LVCMOS
Configuration pin, used in the configuration on power-up of expected input clock
frequency and Resync selection, by connecting to appropriate pin from the CFG_IN[11:0]
pins as required. See PLL Configuration.
16
ALARMC_CO3
O
LVTTL/
LVCMOS
Activity alarm output for the currently selected input reference clock. Active high; high
indicating clock failure. It is also used to configure the device at power-up, where it is
used as a configuration output pin that may be connected to CFG_IN[11:0] input pins as
required. See PLL Configuration.
17
LOCKB
O
Analog
Lock detect output. This is a pulse-width modulated output current, with each pulse
typically +10
μA. The output produces a pulse with a width in proportion to the phase
error seen at the internal phase detector. This pin should be connected via an external
parallel capacitor and resistor to ground. The pin voltage will then give an indication of
phase lock: When low, the device is phase locked; when high the device has frequent
large phase errors and so is not phase locked. The value of the RC components used
determines the time and level of consistency required for lock indication. If LOCKB is
disabled by configuration the LOCKB output is held low.
Table 3 Functional Pins (cont...)
Pin No.
Symbol
I/O
Type
Description
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