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參數(shù)資料
| 型號(hào)： | ACS8947T |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 25/30頁(yè) |
| 文件大小： | 0K |
| 描述： | IC JITTER ATT MULT PLL 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 3G，以太網(wǎng)，PCI，SONET/SDH，無(wú)線系統(tǒng) |
| 輸入： | LVPECL |
| 輸出： | CML，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:4 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 625MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤 |
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ACS8947T JAM PLL
ADVANCED COMMS & SENSING
FINAL
DATASHEET
Revision 1.00/September 2007 Semtech Corp.
Page 4
www.semtech.com
In the I/O column of the pin description tables that follow:
I = input
O = output
I/O = bi-directional
P = power
A = analog
In the Type column:
LVTTL/LVCMOSU = LVTTL/LVCMOS input with pull-up
resistor
LVTTL/LVCMOSD = LVTTL/LVCMOS input with pull
down resistor
Pin Descriptions
Table 1 Power pins
Pin No.
Symbol
I/O
Type
Description
1, 4,
7, 10
VDDO1, VDDO2,
VDDO3, VDDO4
P
-
Independent voltage supplies to power each clock output (differential pair of pins)
OUT1N/P to OUT4N/P respectively. +3.3 V (±5%).
To disable an output and save power, tie associated VDD to 0V.
26
VDDADIV
P
-
Supply voltage for internal dividers in VCO loop, kept as an isolated supply to allow for low
supply noise for the output divider stages. +3.3 V (±5%).
29
VDDP1
P
-
Supply voltage to differential inputs, alarm and configuration pins. +3.3 V (±5%).
43
VDDP2
P
-
Supply voltage to SYNC input and output pins, rate selection pins, input selection pins
and reset pin. +3.3 V (±5%).
34
VDDARF
P
-
Supply voltage for phase and frequency detector (PFD), kept as an isolated supply to
allow for low supply noise. +3.3 V (±5%).
38
VDDOSC
P
-
Supply voltage to the internal VCO. +3.3 V (+5%/-10%).
39
VSSOSC
P
-
Supply ground 0 V for the internal VCO.
49
VSS0
P
-
Common supply ground 0 V.
This is the central leadframe pad on the underside of the package.
Table 2 Internally connected pins
Pin No.
Symbol
I/O
Type
Description
37
IC1
-
Connect to ground.
Table 3 Functional Pins
Pin No.
Symbol
I/O
Type
Description
2OUT1N
O
CML or
LVPECL
One of four CML or LVPECL differential outputs, partnered with pin 3. Programmable at
spot frequencies from 1.23 MHz to 625 MHz. The output frequency is defined by the
configuration pin settings at power up or when RESETB is asserted (logic 0).
See PLL Configuration.
The output is ON when VDD01 is supplied with 3.3 V, or OFF when VDD01 is tied to zero
volts. If VDD01 is connected to 0 V, remove the external biasing resistors.
3OUT1P
O
CML or
LVPECL
CML or LVPECL differential output partnered with pin 2. See pin 2 description for more
detail.
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