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參數(shù)資料
| 型號(hào)： | AC162078 |
| 廠商： | Microchip Technology |
| 文件頁(yè)數(shù)： | 91/318頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | HEADER INTRFC MPLAB ICD2 18F1330 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 附件類型： | 轉(zhuǎn)換接頭 |
| 適用于相關(guān)產(chǎn)品： | ICD2 |
| 產(chǎn)品目錄頁(yè)面： | 658 (CN2011-ZH PDF) |
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PIC18F1230/1330
DS39758D-page 180
2009 Microchip Technology Inc.
17.1
Comparator Configuration
For every analog comparator, there is a control bit
called CMENx in the CMCON register. By setting the
CMENx bit, the corresponding comparator can be
enabled. If the Comparator mode is changed, the
comparator output level may not be valid for the
specified mode change delay shown in Section 23.0
.
17.2
Comparator Operation
A single comparator is shown in Figure 17-1, along with
the relationship between the analog input levels and
the digital output. When the analog input at VIN+
(CMPx) is less than the analog input VIN- (CVREF), the
output of the comparator is a digital low level. When the
analog input at VIN+ (CMPx) is greater than the analog
input VIN- (CVREF), the output of the comparator is a
digital high level. The shaded areas of the output of the
comparator in Figure 17-1 represent the uncertainty
due to input offsets and response time.
17.3
Comparator Reference
In this comparator module, an internal voltage
reference is used (see Section 18.0 “Comparator
).
FIGURE 17-1:
SINGLE COMPARATOR
17.4
Comparator Response Time
Response time is the minimum time, after selecting a
new reference voltage or input source, before the
comparator output has a valid level. If the internal
reference is changed, the maximum delay of the
internal voltage reference must be considered when
using the comparator outputs. Otherwise, the
maximum delay of the comparators should be used
17.5
Comparator Outputs
The comparator outputs are read through the CxOUT
bits of the CMCON register. These bits are read-only.
The uncertainty of each of the comparators is related to
the input offset voltage and the response time given in
the specifications.
17.6
Comparator Interrupts
The comparator interrupt flag is set whenever there is
a change in the output value of the corresponding
comparator. Software will need to maintain information
about the status of the output bits, as read from
CMCON<7:5>, to determine the actual change that
occurred. The CMPxIF bit (PIR1<3:1>) is the
Comparator Interrupt Flag. The CMPxIF bit must be
reset by clearing it. Since it is also possible to write a ‘1’
to this register, a simulated interrupt may be initiated.
Both the CMPxIE bit (PIE1<3:1>) and the PEIE bit
(INTCON<6>) must be set to enable the interrupt for
the corresponding comparator. In addition, the GIE bit
(INTCON<7>) must also be set. If any of these bits are
clear, the interrupt is not enabled, though the CMPxIF
bit will still be set if an interrupt condition occurs.
The user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a) Any read or write of CMCON will end the
mismatch condition.
b) Clear flag bit CMPxIF.
c)
Input returning to original state.
A mismatch condition will continue to set flag bit
CMPxIF. Reading CMCON will end the mismatch
condition and allow flag bit CMPxIF to be cleared.
Note:
Comparator interrupts should be disabled
during a Comparator mode change;
otherwise, a false interrupt may occur.
-
+
VIN+
Output
VIN-
VIN+
VIN-
Note 1:
When reading the PORT register, all pins
configured as analog inputs will read as a
‘0’. Pins configured as digital inputs will
convert an analog input according to the
Schmitt Trigger input specification.
2:
Analog levels on any pin defined as a
digital input may cause the input buffer to
consume more current than is specified.
Note:
If a change in the CMCON register
(C2OUT, C1OUT or C0OUT) should occur
when a read operation is being executed
(start of the Q2 cycle), then the CMPxIF
(PIR1 register) interrupt flag may not get
set.
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