
PIC18F1230/1330
2009 Microchip Technology Inc.
DS39758D-page 87
10.0
I/O PORTS
Depending on the device selected and features
enabled, there are up to five ports available. Some pins
of the I/O ports are multiplexed with an alternate
function from the peripheral features on the device. In
general, when a peripheral is enabled, that pin may not
be used as a general purpose I/O pin.
Each port has three registers for its operation. These
registers are:
TRIS register (Data Direction register)
PORT register (reads the levels on the pins of the
device)
LAT register (Output Latch register)
The Output Latch (LAT register) is useful for read-
modify-write operations on the value that the I/O pins
are driving.
A simplified model of a generic I/O port, without the
FIGURE 10-1:
GENERIC I/O PORT
OPERATION
10.1
PORTA, TRISA and LATA Registers
PORTA is an 8-bit wide, bidirectional port. The
corresponding Data Direction register is TRISA. Setting
a TRISA bit (= 1) will make the corresponding PORTA
pin an input (i.e., put the corresponding output driver in
a high-impedance mode). Clearing a TRISA bit (= 0)
will make the corresponding PORTA pin an output (i.e.,
put the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to it, will write to the port latch.
The Output Latch (LATA) register is also memory
mapped. Read-modify-write operations on the LATA
register read and write the latched output value for
PORTA.
Pins RA6 and RA7 are multiplexed with the main
oscillator pins; they are enabled as oscillator or I/O pins
by the selection of the main oscillator in the Configura-
for details). When they are not used as port pins, RA6
and RA7 and their associated TRIS and LAT bits are
read as ‘0’.
The RA0 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs, one of the
interrupt-on-change inputs and one of the analog
comparator inputs to become RA0/AN0/INT0/KBI0/
CMP0 pin.
The RA1 pin is multiplexed with one of the analog
inputs, one of the external interrupt inputs and one of
the interrupt-on-change inputs to become RA1/AN1/
INT1/KBI1 pin.
Pins RA2 and RA3 are multiplexed with the Enhanced
USART transmission and reception input (see
for details).
The RA4 pin is multiplexed with the Timer0 module
clock input, one of the analog inputs and the analog
VREF+ input to become the RA4/T0CKI/AN2/VREF+ pin.
The Fault detect input for PWM FLTA is multiplexed with
pins RA5 and RA7. Its placement is decided by clearing
or setting the FLTAMX bit of Configuration Register 3H.
The TRISA register controls the direction of the PORTA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 10-1:
INITIALIZING PORTA
Data
Bus
WR LAT
WR TRIS
RD Port
Data Latch
TRIS Latch
RD TRIS
Input
Buffer
I/O pin(1)
Q
D
CK
Q
D
CK
EN
QD
EN
RD LAT
or Port
Note 1:
I/O pins have diode protection to VDD and VSS.
Note:
On a Power-on Reset, RA0, RA1, RA4
and RA5 are configured as analog inputs
and read as ‘0’. RA2 and RA3 are
configured as digital inputs.
CLRF
PORTA
; Initialize PORTA by
; clearing output
; data latches
CLRF
LATA
; Alternate method
; to clear output
; data latches
MOVLW
07h
; Configure A/D
MOVWF
ADCON1
; for digital inputs
MOVWF
07h
; Configure comparators
MOVWF
CMCON
; for digital input
MOVLW
0CFh
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<7:6,3:0> as inputs
; RA<5:4> as outputs