Revision 13 2-79 Timing Characteristics Figure 2-22 Output DDR Timing Diagram 11 6 1 7 2 8 3 910 45 28 " />
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绯诲垪锛� ProASIC3
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闁€鏁�(sh霉)锛� 125000
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ProASIC3 Flash Family FPGAs
Revision 13
2-79
Timing Characteristics
Figure 2-22 Output DDR Timing Diagram
11
6
1
7
2
8
3
910
45
28
3
9
tDDROREMCLR
tDDROHD1
tDDROREMCLR
tDDROHD2
tDDROSUD2
tDDROCLKQ
tDDRORECCLR
CLK
Data_R
Data_F
CLR
Out
tDDROCLR2Q
710
4
Table 2-104 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std. Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
0.70 0.80 0.94
ns
tDDROSUD1
Data_F Data Setup for Output DDR
0.38 0.43 0.51
ns
tDDROSUD2
Data_R Data Setup for Output DDR
0.38 0.43 0.51
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00 0.00 0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00 0.00 0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
0.80 0.91 1.07
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00 0.00 0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.22 0.25 0.30
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.22 0.25 0.30
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR
0.36 0.41 0.48
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR
0.32 0.37 0.43
ns
FDDOMAX
Maximum Frequency for the Output DDR
350
309
263
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
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A3P125-1VQG100T IC FPGA 1KB FLASH 125K 100-VQFP
EPF6016QC240-2N IC FLEX 6000 FPGA 16K 240-RQFP
EPF6016QC240-2 IC FLEX 6000 FPGA 16K 240-RQFP
EP4CE30F29C9LN IC CYCLONE IV FPGA 30K 780FBGA
EP4CE30F29C8N IC CYCLONE IV FPGA 30K 780FBGA
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A3P125-1VQ144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P125-1VQ144I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
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A3P125-1VQ144T 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive ProASIC3 Flash Family FPGAs
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