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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A3P125-1VQ100T |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 137/220闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 125K 100-VQFP |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ProASIC3 |
| RAM 浣嶇附瑷堬細 | 36864 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 71 |
| 闁€鏁�(sh霉)锛� | 125000 |
| 闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
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ProASIC3 Flash Family FPGAs
Revision 13
2-9
Table 2-13 Summary of I/O Output Buffer Power (Per Pin) 鈥� Default I/O Software Settings 1
Applicable to Standard I/O Banks
CLOAD (pF)
VCCI (V)
Static Power
PDC3 (mW) 2
Dynamic Power
PAC10 (W/MHz) 3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
35
3.3
鈥�
431.08
3.3 V LVCMOS Wide Range4
35
3.3
鈥�
431.08
2.5 V LVCMOS
35
2.5
鈥�
247.36
1.8 V LVCMOS
35
1.8
鈥�
128.46
1.5 V LVCMOS (JESD8-11)
35
1.5
鈥�
89.46
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PDC3 is the static power (where applicable) measured on VCCI.
3. PAC10 is the total dynamic power measured on VCC and VCCI.
4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A3P125-1VQG100T | IC FPGA 1KB FLASH 125K 100-VQFP |
| EPF6016QC240-2N | IC FLEX 6000 FPGA 16K 240-RQFP |
| EPF6016QC240-2 | IC FLEX 6000 FPGA 16K 240-RQFP |
| EP4CE30F29C9LN | IC CYCLONE IV FPGA 30K 780FBGA |
| EP4CE30F29C8N | IC CYCLONE IV FPGA 30K 780FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A3P125-1VQ144 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144T | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive ProASIC3 Flash Family FPGAs |
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