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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | A3P125-1VQ100T |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 209/220闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 125K 100-VQFP |
| 妯欐簴鍖呰锛� | 90 |
| 绯诲垪锛� | ProASIC3 |
| RAM 浣嶇附瑷堬細 | 36864 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 71 |
| 闁€鏁�(sh霉)锛� | 125000 |
| 闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
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ProASIC3 Flash Family FPGAs
Revision 13
2-75
Timing Characteristics
Table 2-100 Output Enable Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std. Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.59 0.67 0.79
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36 0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50 0.58
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00 0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76 0.89
ns
tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00 0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25 0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
0.22 0.25 0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.22 0.25 0.30
ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41 0.48
ns
tOECKMPWL Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37 0.43
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A3P125-1VQG100T | IC FPGA 1KB FLASH 125K 100-VQFP |
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| EP4CE30F29C9LN | IC CYCLONE IV FPGA 30K 780FBGA |
| EP4CE30F29C8N | IC CYCLONE IV FPGA 30K 780FBGA |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| A3P125-1VQ144 | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144ES | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144I | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs |
| A3P125-1VQ144T | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive ProASIC3 Flash Family FPGAs |
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