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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A3P125-1VQ100T
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 212/220闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 125K 100-VQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 100-TQFP
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ProASIC3 Flash Family FPGAs
Revision 13
2-77
Timing Characteristics
Figure 2-20 Input DDR Timing Diagram
tDDRICLR2Q2
tDDRIREMCLR
tDDRIRECCLR
tDDRICLR2Q1
12
3
4
5
6
7
8
9
CLK
Data
CLR
Out_QR
Out_QF
tDDRICLKQ1
2
4
6
3
5
7
tDDRIHD
tDDRISUD
tDDRICLKQ2
Table 2-102 Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.27
0.31
0.37
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.39
0.44
0.52
ns
tDDRISUD
Data Setup for Input DDR (Fall)
0.25
0.28
0.33
ns
Data Setup for Input DDR (Rise)
0.25
0.28
0.33
ns
tDDRIHD
Data Hold for Input DDR (Fall)
0.00
ns
Data Hold for Input DDR (Rise)
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
0.46
0.53
0.62
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
0.57
0.65
0.76
ns
tDDRIREMCLR
Asynchronous Clear Removal time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery time for Input DDR
0.22
0.25
0.30
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.22
0.25
0.30
ns
tDDRICKMPWH Clock Minimum Pulse Width High for Input DDR
0.36
0.41
0.48
ns
tDDRICKMPWL Clock Minimum Pulse Width Low for Input DDR
0.32
0.37
0.43
ns
FDDRIMAX
Maximum Frequency for Input DDR
350
309
263
MHz
Note: For specific junction temperature and voltage-supply levels, refer to Table 2-6 on page 2-6 for derating values.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3P125-1VQG100T IC FPGA 1KB FLASH 125K 100-VQFP
EPF6016QC240-2N IC FLEX 6000 FPGA 16K 240-RQFP
EPF6016QC240-2 IC FLEX 6000 FPGA 16K 240-RQFP
EP4CE30F29C9LN IC CYCLONE IV FPGA 30K 780FBGA
EP4CE30F29C8N IC CYCLONE IV FPGA 30K 780FBGA
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A3P125-1VQ144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
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