Revision 13 2-31 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor鈥揟ransistor " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� A3P125-1VQ100T
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 161/220闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 125K 100-VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� ProASIC3
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 71
闁€鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 125°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
绗�1闋�(y猫)绗�2闋�(y猫)绗�3闋�(y猫)绗�4闋�(y猫)绗�5闋�(y猫)绗�6闋�(y猫)绗�7闋�(y猫)绗�8闋�(y猫)绗�9闋�(y猫)绗�10闋�(y猫)绗�11闋�(y猫)绗�12闋�(y猫)绗�13闋�(y猫)绗�14闋�(y猫)绗�15闋�(y猫)绗�16闋�(y猫)绗�17闋�(y猫)绗�18闋�(y猫)绗�19闋�(y猫)绗�20闋�(y猫)绗�21闋�(y猫)绗�22闋�(y猫)绗�23闋�(y猫)绗�24闋�(y猫)绗�25闋�(y猫)绗�26闋�(y猫)绗�27闋�(y猫)绗�28闋�(y猫)绗�29闋�(y猫)绗�30闋�(y猫)绗�31闋�(y猫)绗�32闋�(y猫)绗�33闋�(y猫)绗�34闋�(y猫)绗�35闋�(y猫)绗�36闋�(y猫)绗�37闋�(y猫)绗�38闋�(y猫)绗�39闋�(y猫)绗�40闋�(y猫)绗�41闋�(y猫)绗�42闋�(y猫)绗�43闋�(y猫)绗�44闋�(y猫)绗�45闋�(y猫)绗�46闋�(y猫)绗�47闋�(y猫)绗�48闋�(y猫)绗�49闋�(y猫)绗�50闋�(y猫)绗�51闋�(y猫)绗�52闋�(y猫)绗�53闋�(y猫)绗�54闋�(y猫)绗�55闋�(y猫)绗�56闋�(y猫)绗�57闋�(y猫)绗�58闋�(y猫)绗�59闋�(y猫)绗�60闋�(y猫)绗�61闋�(y猫)绗�62闋�(y猫)绗�63闋�(y猫)绗�64闋�(y猫)绗�65闋�(y猫)绗�66闋�(y猫)绗�67闋�(y猫)绗�68闋�(y猫)绗�69闋�(y猫)绗�70闋�(y猫)绗�71闋�(y猫)绗�72闋�(y猫)绗�73闋�(y猫)绗�74闋�(y猫)绗�75闋�(y猫)绗�76闋�(y猫)绗�77闋�(y猫)绗�78闋�(y猫)绗�79闋�(y猫)绗�80闋�(y猫)绗�81闋�(y猫)绗�82闋�(y猫)绗�83闋�(y猫)绗�84闋�(y猫)绗�85闋�(y猫)绗�86闋�(y猫)绗�87闋�(y猫)绗�88闋�(y猫)绗�89闋�(y猫)绗�90闋�(y猫)绗�91闋�(y猫)绗�92闋�(y猫)绗�93闋�(y猫)绗�94闋�(y猫)绗�95闋�(y猫)绗�96闋�(y猫)绗�97闋�(y猫)绗�98闋�(y猫)绗�99闋�(y猫)绗�100闋�(y猫)绗�101闋�(y猫)绗�102闋�(y猫)绗�103闋�(y猫)绗�104闋�(y猫)绗�105闋�(y猫)绗�106闋�(y猫)绗�107闋�(y猫)绗�108闋�(y猫)绗�109闋�(y猫)绗�110闋�(y猫)绗�111闋�(y猫)绗�112闋�(y猫)绗�113闋�(y猫)绗�114闋�(y猫)绗�115闋�(y猫)绗�116闋�(y猫)绗�117闋�(y猫)绗�118闋�(y猫)绗�119闋�(y猫)绗�120闋�(y猫)绗�121闋�(y猫)绗�122闋�(y猫)绗�123闋�(y猫)绗�124闋�(y猫)绗�125闋�(y猫)绗�126闋�(y猫)绗�127闋�(y猫)绗�128闋�(y猫)绗�129闋�(y猫)绗�130闋�(y猫)绗�131闋�(y猫)绗�132闋�(y猫)绗�133闋�(y猫)绗�134闋�(y猫)绗�135闋�(y猫)绗�136闋�(y猫)绗�137闋�(y猫)绗�138闋�(y猫)绗�139闋�(y猫)绗�140闋�(y猫)绗�141闋�(y猫)绗�142闋�(y猫)绗�143闋�(y猫)绗�144闋�(y猫)绗�145闋�(y猫)绗�146闋�(y猫)绗�147闋�(y猫)绗�148闋�(y猫)绗�149闋�(y猫)绗�150闋�(y猫)绗�151闋�(y猫)绗�152闋�(y猫)绗�153闋�(y猫)绗�154闋�(y猫)绗�155闋�(y猫)绗�156闋�(y猫)绗�157闋�(y猫)绗�158闋�(y猫)绗�159闋�(y猫)绗�160闋�(y猫)鐣�(d膩ng)鍓嶇161闋�(y猫)绗�162闋�(y猫)绗�163闋�(y猫)绗�164闋�(y猫)绗�165闋�(y猫)绗�166闋�(y猫)绗�167闋�(y猫)绗�168闋�(y猫)绗�169闋�(y猫)绗�170闋�(y猫)绗�171闋�(y猫)绗�172闋�(y猫)绗�173闋�(y猫)绗�174闋�(y猫)绗�175闋�(y猫)绗�176闋�(y猫)绗�177闋�(y猫)绗�178闋�(y猫)绗�179闋�(y猫)绗�180闋�(y猫)绗�181闋�(y猫)绗�182闋�(y猫)绗�183闋�(y猫)绗�184闋�(y猫)绗�185闋�(y猫)绗�186闋�(y猫)绗�187闋�(y猫)绗�188闋�(y猫)绗�189闋�(y猫)绗�190闋�(y猫)绗�191闋�(y猫)绗�192闋�(y猫)绗�193闋�(y猫)绗�194闋�(y猫)绗�195闋�(y猫)绗�196闋�(y猫)绗�197闋�(y猫)绗�198闋�(y猫)绗�199闋�(y猫)绗�200闋�(y猫)绗�201闋�(y猫)绗�202闋�(y猫)绗�203闋�(y猫)绗�204闋�(y猫)绗�205闋�(y猫)绗�206闋�(y猫)绗�207闋�(y猫)绗�208闋�(y猫)绗�209闋�(y猫)绗�210闋�(y猫)绗�211闋�(y猫)绗�212闋�(y猫)绗�213闋�(y猫)绗�214闋�(y猫)绗�215闋�(y猫)绗�216闋�(y猫)绗�217闋�(y猫)绗�218闋�(y猫)绗�219闋�(y猫)绗�220闋�(y猫)
ProASIC3 Flash Family FPGAs
Revision 13
2-31
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor鈥揟ransistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer.
Table 2-37 Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
27
25
10 10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
27
25
10 10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
54
51
10 10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
54
51
10 10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12 12
109
103
10 10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16 16
127
132
10 10
24 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
24 24
181
268
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Table 2-38 Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
27
25
10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
27
25
10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
54
51
10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
54
51
10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12
109
103
10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16
109
103
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A3P125-1VQG100T IC FPGA 1KB FLASH 125K 100-VQFP
EPF6016QC240-2N IC FLEX 6000 FPGA 16K 240-RQFP
EPF6016QC240-2 IC FLEX 6000 FPGA 16K 240-RQFP
EP4CE30F29C9LN IC CYCLONE IV FPGA 30K 780FBGA
EP4CE30F29C8N IC CYCLONE IV FPGA 30K 780FBGA
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A3P125-1VQ144 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P125-1VQ144ES 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P125-1VQ144I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P125-1VQ144PP 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:ProASIC3 Flash Family FPGAs
A3P125-1VQ144T 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Automotive ProASIC3 Flash Family FPGAs