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參數(shù)資料
| 型號(hào)： | 952801CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 293.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | MO-118, GREEN, SSOP-48 |
| 文件頁(yè)數(shù)： | 7/24頁(yè) |
| 文件大小： | 219K |
| 代理商： | 952801CFLFT |
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15
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
I
2C Table: Slew Rate Control Register
Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
24/48Slw1
RW
-
0
Bit 6
24/48Slw0
RW
-
0
Bit 5
AGPSlw1
RW
-
0
Bit 4
AGPSlw0
RW
-
0
Bit 3
ZCLKSlw1
RW
-
0
Bit 2
ZCLKSlw0
RW
-
0
Bit 1
REFSlw1
RW
-
0
Bit 0
REFSlw0
RW
-
0
I
2C Table: Slew Rate Control Register
Control
Function
Bit 7
SDSlw1
RW
-
0
Bit 6
SDSlw0
RW
-
0
Bit 5
AGPCLK1
Output Control
RW
Disable
Enable
1
Bit 4
AGPCLK0
Output Control
RW
Disable
Enable
1
Bit 3
PCI_FSlw1
RW
-
0
Bit 2
PCI_FSlw0
RW
-
0
Bit 1
PCISlw1
RW
-
0
Bit 0
PCISlw0
RW
-
0
I
2C Table: Output Control Register
Control
Function
Bit 7
Reserved
RW
-
0
Bit 6
SEL24_48
24MHz or 48MHz
RW
48MHz
24MHz
1
Bit 5
Reserved
RW
-
1
Bit 4
48MHz
Output Control
RW
Disable
Enable
1
Bit 3
24_48MHz
Output Control
RW
Disable
Enable
1
Bit 2
REF2
Output Control
RW
Disable
Enable
1
Bit 1
REF1
Output Control
RW
Disable
Enable
1
Bit 0
REF0
Output Control
RW
Disable
Enable
1
I
2C Table: Reserved Register
Control
Function
Bit 7
Reserved
RW
-
0
Bit 6
FS6
Freq Select bit 6
RW
0
Bit 5
FS5
Freq Select bit 5
RW
0
Bit 4
Reserved
RW
-
0
Bit 3
Reserved
RW
-
0
Bit 2
SS_SEL
SS Scheme Select1
RW
0
Bit 1
SS_SEL
SS Scheme Select1
RW
0
Bit 0
Reserved
RW
-
0
Byte 21
-
24/48 Slew Rate
Control
AGP Slew Rate Control
-
ZCLK Slew Rate
Control
REF Slew Rate Control
PWD
-
Byte 22
Pin #
Name
Type
1
0
34
35
-
1
0PWD
-
Byte 23
Pin #
Name
Type
4
3
2
-
30
29
-
See Table 1
-
PWD
-
Byte 24
Pin #
Name
Type
See Table 2: Spread
Spectrum Selection Table
PCI Slew Rate Control
PCI_F Slew Rate
Control
SD Slew Rate Control
01
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