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參數(shù)資料
| 型號： | 952801CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 293.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | MO-118, GREEN, SSOP-48 |
| 文件頁數(shù)： | 2/24頁 |
| 文件大小： | 219K |
| 代理商： | 952801CFLFT |
10
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
I
2C Table: Reserved Register
Control
Function
Bit 7
Reserved
RW
-
1
Bit 6
Reserved
RW
-
1
Bit 5
Reserved
RW
-
1
Bit 4
Reserved
RW
-
1
Bit 3
Reserved
RW
-
1
Bit 2
Reserved
RW
-
1
Bit 1
Reserved
RW
-
1
Bit 0
Reserved
RW
-
1
I
2C Table: Frequency Select Register
Control
Function
Bit 7
FS3
Freq Select Bit 7
RW
0
Bit 6
FS2
Freq Select Bit 6
RW
0
Bit 5
FS1
Freq Select Bit 5
RW
0
Bit 4
FS0
Freq Select Bit 4
RW
0
Bit 3
FS Source
Frequency HW/IIC
Select
RW
Latch Input
IIC
0
Bit 2
FS4
Freq Select Bit 2
RW
0
Bit 1
SS_EN
Spread Enable
RW
OFF
ON
1
Bit 0
Outputs
Output Control
RW
Running
Tri-state
0
I
2C Table: Read Back Register
Control
Function
Bit 7
WDHRB
WD Hard Alarm Status
Read back
RNormal
Alarm
X
Bit 6
WDSRB
WD Soft Alarm Status
Read back
RNormal
Alarm
X
Bit 5
MULTISEL
Multisel Read back
R
-
X
Bit 4
FS4RB
FS4 Read back
R
-
X
Bit 3
FS3RB
FS3 Read back
R
-
X
Bit 2
FS2RB
FS2 Read back
R
-
X
Bit 1
FS1RB
FS1 Read back
R
-
X
Bit 0
FS0RB
FS0 Read back
R
-
X
I
2C Table: Output Control Register
Control
Function
Bit 7
ZCLK_1
Output Control
RW
Disable
Enable
1
Bit 6
ZCLK_0
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK_F0
PCI_STOP# Control
RW
Stop Disable Stop Enable
0
Bit 4
PCICLK_F1
PCI_STOP# Control
RW
Stop Disable Stop Enable
0
Bit 3
CPUCLK8T0/C0
CPU_STOP# Control
RW
Stop Disable Stop Enable
1
Bit 2
CPUCLK8T1/C1
CPU_STOP# Control
RW
Stop Disable Stop Enable
1
Bit 1
CPUCLK8T0/C0
Output Control
RW
Disable
Enable
1
Bit 0
CPUCLK8T1/C1
Output Control
RW
Disable
Enable
1
Type
See Table1 : Quad Rom
Frequency Selection Table
See Table1
01
0
1
0PWD
PWD
1
PWD
Name
Type
1
0
Byte 3
Pin #
-
Name
Type
Byte 4
Pin #
-
Byte 5
Pin #
Name
-
Name
9
42, 41
46, 45
13
14
10
Byte 6
Pin #
42, 41
46, 45
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