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參數(shù)資料
| 型號： | 952801CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 293.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | MO-118, GREEN, SSOP-48 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 952801CFLFT |
13
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
Reserved
RW
-
X
Bit 6
Reserved
RW
-
X
Bit 5
Reserved
RW
-
X
Bit 4
Reserved
RW
-
X
Bit 3
CPU Div3
RW
X
Bit 2
CPU Div2
RW
X
Bit 1
CPU Div1
RW
X
Bit 0
CPU Div0
RW
X
01
PWD
-
Type
-
Byte 15
Pin #
Name
-
CPU divider ratio can
be configured via these
4 bits individually.
See Table 5: Divider Ratio
Combination Table
-
Table 5: CPU Divider Ratio Combination Table
Bit
00011011
MSB
1248
00
0000
2
0100
4
1000
8
1100
16
01
0001
3
0101
6
1001
12
1101
24
10
0010
5
0110
10
1010
20
1110
40
11
0011
7
0111
14
1011
28
1111
56
LSB
Address
Div
Address
Div
Address
Div
Address
Div
Divider (3:2)
Divider
(1:0)
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
Reserved
RW
-
X
Bit 6
Reserved
RW
-
X
Bit 5
Reserved
RW
-
X
Bit 4
Reserved
RW
-
X
Bit 3
Reserved
RW
-
X
Bit 2
Reserved
RW
-
X
Bit 1
Reserved
RW
-
X
Bit 0
Reserved
RW
-
X
I
2C Table: Output Divider Control Register
Control
Function
Bit 7
Reserved
RW
-
X
Bit 6
Reserved
RW
-
X
Bit 5
Reserved
RW
-
X
Bit 4
CPUINV
CPU Phase Invert
RW
Default
Inverse
X
Bit 3
Reserved
RW
-
X
Bit 2
Reserved
RW
-
X
Bit 1
Reserved
RW
-
X
Bit 0
Reserved
RW
-
X
PWD
-
Type
0
1
-
Byte 16
Pin #
Name
-
01
PWD
-
Byte 17
Pin #
Name
Type
-
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