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參數(shù)資料
| 型號： | 952801CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 293.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | MO-118, GREEN, SSOP-48 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 952801CFLFT |
2
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
The ICS952801 is a two chip clock solution for desktop designs using SIS 755/760 style chipsets. When used with a zero
delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks
signals for such a system.
The ICS952801 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the
use of a serially programmable I
2C interface, this device can adjust the output clocks by configuring the frequency setting, the
output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
Block Diagram
Power Groups
VDD
GND
1
5
REF Output, Crystal
31
28
24/48MHz, Fix Analog, Fix Digital
38
36
CPU PLL, CPU Analog, MCLK
Pin Number
Description
CPUCLK8T (1:0)
AGPCLK (1:0)
PCICLK (5:0)
PCICLKF (1:0)
ZCLK (1:0)
CPUCLK8C (1:0)
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz
24_48MHz
X1
X2
XTAL
PD#
CPU_STOP#
PCI_STOP#
FS (4:0)
SEL24_48MHZ
Control
Logic
REF (2:0)
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