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參數(shù)資料
| 型號： | 952801CFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 293.34 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | MO-118, GREEN, SSOP-48 |
| 文件頁數(shù)： | 24/24頁 |
| 文件大?。?/td> | 219K |
| 代理商： | 952801CFLFT |
9
Integrated
Circuit
Systems, Inc.
ICS952801
Advance Information
0719—01/22/03
I
2C Table: Function Control Register
Control
Function
Bit 7
PDEN
PD# Enable
RW
Disable
Enable
1
Bit 6
PCICLK7
Output Control
RW
Disable
Enable
1
Bit 5
WDS_EN
WD Soft Enable
RW
Disable
Enable
1
Bit 4
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 3
AFS1
Async Rom SEL_1
RW
0
Bit 2
AFS0
Async Rom SEL_0
RW
0
Bit 1
AEN1
RW
0
Bit 0
AEN0
RW
0
Zclk/Agp/Pci Freq
Source Select Control
See Table 3: Async Z-CLK
Frequency Selection Table
See Table 4 : ZCLK, AGP &
PCI Frequency Source
Decode Table
-
25
-
1PWD
-
26
Name
Pin #
Byte 0
Type
0
Table 3: Asynchronous ZCLK Frequency Selection Table
Table 4: ZCLK, AGP & PCI Frequency Source Decode Table
Byte0 Bit3
Byte0 Bit2
ZCLK Frequency
Byte0 Bit1
Byte0 Bit0
ZCLK & AGP & PCI
0
64.01
0
See Table 1, QuadRom
Frequency Table
0
1
72.01
0
1
N-Programming for
AGP/PCI/ZCLK
1
0
82.30
1
0
See Table 1 for AGP/PCI,
Table 3 for ZCLK
1
144.02
1
N-Programming for AGP/PCI,
Table 3 for ZCLK
I
2C Table: Async N-Programming Frequency Select Register
Control
Function
Bit 7
N PLL3 Div7
RW
-
0
Bit 6
N PLL3 Div6
RW
-
1
Bit 5
N PLL3 Div5
RW
-
0
Bit 4
N PLL3 Div4
RW
-
0
Bit 3
N PLL3 Div3
RW
-
0
Bit 2
N PLL3 Div2
RW
-
1
Bit 1
N PLL3 Div1
RW
-
1
Bit 0
N PLL3 Div0
RW
-
1
I
2C Table: Reserved Register
Control
Function
Bit 7
Reserved
RW
-
1
Bit 6
Reserved
RW
-
1
Bit 5
Reserved
RW
-
1
Bit 4
Reserved
RW
-
1
Bit 3
Reserved
RW
-
1
Bit 2
Reserved
RW
-
1
Bit 1
Reserved
RW
-
1
Bit 0
Reserved
RW
-
1
The decimal
representation of N
PLL2 Div (7:0) + 8 is
equal to VCO divider
value for PLL2. Default
at power up =
66.67MHz
-
Name
-
1
1PWD
0
Type
PWD
0
-
Name
Type
Byte 2
-
Pin #
-
Pin #
-
Byte 1
-
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