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參數(shù)資料
| 型號： | 951462YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 |
| 文件頁數(shù)： | 7/23頁 |
| 文件大小： | 241K |
| 代理商： | 951462YGLFT |
15
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
Absolute Maximum Rating (Above which useful life may be impaired)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
3.3V Core Supply Voltage
VDD_A
-
V
DD + 0.5V
V
1
3.3V Logic Input Supply
Voltage
VDD_In
-
GND -
0.5
V
DD + 0.5V
V
1
Storage Temperature
Ts
-
-65
150
°C1
Ambient Operating Temp
Tambient
-
0
70
°C
1
Max Junction Temp
T
J
V
DD MAX, 70°C
130
°C
1
Case Temperature
Tcase
-
115
°C
1
Input ESD protection HBM
ESD prot
-
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS
Notes
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD + 0.3
V
1
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS - 0.3
0.8
V
1
Input High Current
I
IH
V
IN = VDD
-5
5
uA
1
I
IL1
V
IN = 0 V; Inputs with no pull-up
resistors
-5
uA
1
I
IL2
V
IN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Low Threshold Input-
High Voltage
V
IH_FS
3.3 V +/-5%
0.7
V
DD + 0.3
V
1
Low Threshold Input-
Low Voltage
V
IL_FS
3.3 V +/-5%
V
SS - 0.3
0.35
V
1
Operating Current
I
DD3.3OP
all outputs driven
400
mA
1
all diff pairs driven
70
mA
1
all differential pairs tri-stated
12
mA
1
Input Frequency
F
i
V
DD = 3.3 V
14.31818
MHz
2
Pin Inductance
L
pin
7nH
1
C
IN
Logic Inputs
5
pF
1
C
OUT
Output pin capacitance
6
pF
1
C
INX
X1 & X2 pins
5
pF
1
Clk Stabilization
T
STAB
From VDD Power-Up or de-
assertion of PD to 1st clock
1.8
ms
1
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_PD
CPU output enable after
PD de-assertion
300
us
1
Tfall_PD
PD fall time of
5
ns
1
Trise_PD
PD rise time of
5
ns
1
SMBus Voltage
V
DD
2.7
5.5
V
1
Low-level Output Voltage
V
OL
@ I
PULLUP
0.4
V
1
Current sinking at
V
OL = 0.4 V
I
PULLUP
4mA
1
SMBCLK/SMBDAT
Clock/Data Rise Time
T
RI2C
(Max VIL - 0.15) to
(Min VIH + 0.15)
1000
ns
1
SMBCLK/SMBDAT
Clock/Data Fall Time
T
FI2C
(Min VIH + 0.15) to
(Max VIL - 0.15)
300
ns
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
1Guaranteed by design and characterization, not 100% tested in production.
Input Low Current
Powerdown Current
I
DD3.3PD
Input Capacitance
2 Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL
outputs.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 951463AGLF | 制造商:Integrated Device Technology Inc 功能描述:951463AGLF - Rail/Tube |
| 951463BFLF | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:56 SSOP (LEAD FREE) - Rail/Tube |
| 951463BFLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:56 SSOP (LEAD FREE) - Tape and Reel |
| 951463BGLF | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK |
| 951463BGLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK |
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