參數(shù)資料
型號: 951462YGLFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁數(shù): 10/23頁
文件大小: 241K
代理商: 951462YGLFT
18
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
Electrical Characteristics - REF-14.318MHz
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
Clock period
T
period
14.318MHz output nominal
69.8270
69.8550
ns
2
Clock Low Time
T
low
Measure from < 0.6V
30.9290
37.9130
ns
2
Clock High Time
T
high
Measure from > 2.0V
30.9290
37.9130
ns
2
Output High Voltage
V
OH
I
OH = -1 mA
2.4
V
1
Output Low Voltage
V
OL
I
OL = 1 mA
0.4
V
1
Output High Current
I
OH
V
OH @MIN = 1.0 V,
V
OH@MAX = 3.135 V
-29
-23
mA
1
Output Low Current
I
OL
V
OL @MIN = 1.95 V,
V
OL @MAX = 0.4 V
29
27
mA
1
Rise Time
t
r1
V
OL = 0.4 V, VOH = 2.4 V
1.5
ns
1
Fall Time
t
f1
V
OH = 2.4 V, VOL = 0.4 V
1.5
ns
1
Skew
t
sk1
V
T = 1.5 V
100
ps
1
Duty Cycle
d
t1
V
T = 1.5 V
44
53
56
%
1
Jitter
t
jcyc-cyc
V
T = 1.5 V
200
300
ps
1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22 (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
Electrical Characteristics - USB - 48MHz
PARAMETER
SYMBOL
CONDITIONS*
MIN
TYP
MAX
UNITS NOTES
Long Accuracy
ppm
see Tperiod min-max values
-100
100
ppm
1,2
Clock period
T
period
48.00MHz output nominal
20.8229
20.8344
ns
2
Clock Low Time
T
low
Measure from < 0.6V
9.3750
11.4580
ns
2
Clock High Time
T
high
Measure from > 2.0V
9.3750
11.4580
ns
2
Output High Voltage
V
OH
I
OH = -1 mA
2.4
V
1
Output Low Voltage
V
OL
I
OL = 1 mA
0.55
V
1
V
OH @MIN = 1.0 V
-33
mA
1
V
OH@MAX = 3.135 V
-33
mA
1
V
OL @ MIN = 1.95 V
30
mA
1
V
OL @ MAX = 0.4 V
38
mA
1
Rise Time
t
r_USB
V
OL = 0.4 V, VOH = 2.4 V
0.5
1.5
ns
1
Fall Time
t
f_USB
V
OH = 2.4 V, VOL = 0.4 V
0.5
1.5
ns
1
Duty Cycle
d
t1
V
T = 1.5 V
45
55
%
1
Group Skew
t
skew
V
T = 1.5 V
100
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
V
T = 1.5 V
130
ps
1,2
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs = 22 (unless otherwise specified)
1Guaranteed by design and characterization, not 100% tested in production.
2ICS recommended and/or chipset vendor layout guidelines must be followed to meet this specification
Output High Current
I
OH
Output Low Current
I
OL
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