參數(shù)資料
型號(hào)： 951462YGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, PDSO64
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64
文件頁(yè)數(shù)： 2/23頁(yè)
文件大?。?/td> 241K
代理商： 951462YGLFT
10
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
SMBus Table: Spread Spectrum Enable and CPU Frequency Select Register
Byte 0
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
-FS Source
Latched Input or SMBus
Frequency Select
RW
Latched
Inputs
SMBus
0
Bit 6
-
ATIG SS_EN
ATIG Spread Spectrum Enable
RW
Disable
Enable
0
Bit 5
-
SRC SS_EN
SRC Spread Spectrum Enable
RW
Disable
Enable
0
Bit 4
-
CPU SS_EN
CPU Spread Spectrum Enable
RW
Disable
Enable
0
Bit 3
-
CPU FS3
CPU Freq Select Bit 3
RW
0
Bit 2
-
CPU FS2
CPU Freq Select Bit 2
RW
Latch
Bit 1
-
CPU FS1
CPU Freq Select Bit 1
RW
Latch
Bit 0
-
CPU FS0
CPU Freq Select Bit 0
RW
Latch
Note: Each Spread Spectrum Enable bit is independent from the other.
Bit(6:4) must all set to "1" in order to enable spread for CPU, SRC and ATIG clocks.
SMBus Table: Output Control Register
Byte 1
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
7
48MHz_1
48MHz_1 Output Enable
RW
Disable
Enable
1
Bit 6
6
48MHz_0
48MHz_0 Output Enable
RW
Disable
Enable
1
Bit 5
62
REF2
REF2 Output Enable
RW
Disable
Enable
1
Bit 4
63
REF1
REF1 Output Enable
RW
Disable
Enable
1
Bit 3
64
REF0
REF0 Output Enable
RW
Disable
Enable
1
Bit 2
59
HTTCLK0
HTTCLK0 Output Enable
RW
Disable
Enable
1
Bit 1
52,51
CPUCLK1
CPUCLK1 Output Enable
RW
Disable
Enable
1
Bit 0
56,55
CPUCLK0
CPUCLK0 Output Enable
RW
Disable
Enable
1
SMBus Table: ATIGCLK and CLKREQB# Output Control Register
Byte 2
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
30,31
ATIGCLK3
ATIGCLK3 Output Enable
RW
Disable
Enable
1
Bit 6
35,34
ATIGCLK2
ATIGCLK2 Output Enable
RW
Disable
Enable
1
Bit 5
37,36
ATIGCLK1
ATIGCLK1 Output Enable
RW
Disable
Enable
1
Bit 4
41,40
ATIGCLK0
ATIGCLK0 Output Enable
RW
Disable
Enable
1
Bit 3
20,21
REQBSRC4
CLKREQB# Controls SRC4
RW
Does not
control
Controls
0
Bit 2
24,25
REQBSRC3
CLKREQB# Controls SRC3
RW
Does not
control
Controls
0
Bit 1
26,27
REQBSRC2
CLKREQB# Controls SRC2
RW
Does not
control
Controls
0
Bit 0
30,31
REQBATIG3
CLKREQB# Controls ATIG3
RW
Does not
control
Controls
0
SMBus Table: SRCCLK Output Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
12,13
SRCCLK7
RW
Disable
Enable
1
Bit 6
16,17
SRCCLK6
RW
Disable
Enable
1
Bit 5
18,19
SRCCLK5
RW
Disable
Enable
1
Bit 4
20,21
SRCCLK4
RW
Disable
Enable
1
Bit 3
24,25
SRCCLK3
RW
Disable
Enable
1
Bit 2
26,27
SRCCLK2
RW
Disable
Enable
1
Bit 1
43,42
SRCCLK1
RW
Disable
Enable
1
Bit 0
47,46
SRCCLK0
RW
Disable
Enable
1
See Table 1:
CPU Frequency Selection
Table
Master Output control. Enables
or disables output, regardless of
CLKREQ# inputs.
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