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參數(shù)資料
| 型號： | 951462YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 241K |
| 代理商： | 951462YGLFT |
3
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
33
*CLKREQC#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
34
ATIGCLKC2
OUT
Complementary clock of differential ATIGCLK clock pair.
35
ATIGCLKT2
OUT
True clock of differential ATIGCLK clock pair.
36
ATIGCLKC1
OUT
Complementary clock of differential ATIGCLK clock pair.
37
ATIGCLKT1
OUT
True clock of differential ATIGCLK clock pair.
38
GNDATIG
PWR
Ground for ATIG clocks
39
VDDATIG
PWR
Power supply ATIG clocks, nominal 3.3V
40
ATIGCLKC0
OUT
Complementary clock of differential ATIGCLK clock pair.
41
ATIGCLKT0
OUT
True clock of differential ATIGCLK clock pair.
42
SRCCLKC1
OUT
Complement clock of differential push-pull SRC clock pair.
43
SRCCLKT1
OUT
True clock of differential SRC clock pair.
44
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
45
GNDSRC
PWR
Ground pin for the SRC outputs
46
SRCCLKC0
OUT
Complement clock of differential SRC clock pair.
47
SRCCLKT0
OUT
True clock of differential SRC clock pair.
48
IREF
OUT
This pin establishes the reference current for the differential current-mode
output pairs. This pin requires a fixed precision resistor tied to ground in
order to establish the appropriate current. 475 ohms is the standard value.
49
GNDA
PWR
Ground pin for the PLL core.
50
VDDA
PWR
3.3V power for the PLL core.
51
CPUCLK8C1
OUT
Complementary clock of differential 3.3V push-pull K8 pair.
52
CPUCLK8T1
OUT
True clock of differential 3.3V push-pull K8 pair.
53
GNDCPU
PWR
Ground pin for the CPU outputs
54
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
55
CPUCLK8C0
OUT
Complementary clock of differential 3.3V push-pull K8 pair.
56
CPUCLK8T0
OUT
True clock of differential 3.3V push-pull K8 pair.
57
*CLKREQA#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
58
GNDHTT
PWR
Ground pin for the HTT outputs
59
HTTCLK0
OUT
3.3V Hyper Transport output
60
VDDHTT
PWR
Supply for HTT clocks, nominal 3.3V.
61
PD**
IN
Asynchronous active high input pin used to power down the device. The
internal clocks are disabled and the VCO is stopped.
62
FS2/REF2
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
63
FS1/REF1
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
64
FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
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| 951 | WIRE TERMINAL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 951463AGLF | 制造商:Integrated Device Technology Inc 功能描述:951463AGLF - Rail/Tube |
| 951463BFLF | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:56 SSOP (LEAD FREE) - Rail/Tube |
| 951463BFLFT | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK 制造商:Integrated Device Technology Inc 功能描述:56 SSOP (LEAD FREE) - Tape and Reel |
| 951463BGLF | 制造商:Integrated Device Technology Inc 功能描述:PC MAIN CLOCK |
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