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參數(shù)資料
| 型號(hào)： | 951462YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PDSO64 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-64 |
| 文件頁(yè)數(shù)： | 12/23頁(yè) |
| 文件大?。?/td> | 241K |
| 代理商： | 951462YGLFT |
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2
Integrated
Circuit
Systems, Inc.
ICS951462
1094J—03/16/09
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
1
GNDREF
PWR
Ground pin for the REF outputs.
2
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT
Crystal output, Nominally 14.318MHz
5
VDD48
PWR
Power pin for the 48MHz output.3.3V
6
48MHz_0
OUT
48MHz clock output.
7
48MHz_1
OUT
48MHz clock output.
8
GND48
PWR
Ground pin for the 48MHz outputs
9
SMBCLK
IN
Clock pin of SMBUS circuitry, 5V tolerant
10
SMBDAT
I/O
Data pin of SMBUS circuitry, 5V tolerant
11
RESET_IN#
IN
Real time active low input. When active, SMBus is reset to power up
default.
12
SRCCLKT7
OUT
True clock of differential SRC clock pair.
13
SRCCLKC7
OUT
Complement clock of differential SRC clock pair.
14
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
15
GNDSRC
PWR
Ground pin for the SRC outputs
16
SRCCLKT6
OUT
True clock of differential SRC clock pair.
17
SRCCLKC6
OUT
Complement clock of differential SRC clock pair.
18
SRCCLKT5
OUT
True clock of differential SRC clock pair.
19
SRCCLKC5
OUT
Complement clock of differential SRC clock pair.
20
SRCCLKT4
OUT
True clock of differential SRC clock pair.
21
SRCCLKC4
OUT
Complement clock of differential SRC clock pair.
22
GNDSRC
PWR
Ground pin for the SRC outputs
23
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
24
SRCCLKT3
OUT
True clock of differential SRC clock pair.
25
SRCCLKC3
OUT
Complement clock of differential SRC clock pair.
26
SRCCLKT2
OUT
True clock of differential SRC clock pair.
27
SRCCLKC2
OUT
Complement clock of differential SRC clock pair.
28
VDDSRC
PWR
Supply for SRC clocks, 3.3V nominal
29
GNDSRC
PWR
Ground pin for the SRC outputs
30
ATIGCLKT3
OUT
True clock of differential ATIGCLK clock pair.
31
ATIGCLKC3
OUT
Complementary clock of differential ATIGCLK clock pair.
32
*CLKREQB#
IN
Output enable for PCI Express (SRC) outputs. SMBus selects which
outputs are controlled.
0 = enabled, 1 = tri-stated
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| 951 | WIRE TERMINAL |
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| 951463AGLF | 制造商:Integrated Device Technology Inc 功能描述:951463AGLF - Rail/Tube |
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