參數(shù)資料
型號： 935266671518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁數(shù)： 73/83頁
文件大?。?/td> 316K
代理商： 935266671518
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
72
15.0
AC CHARACTERISTICS
GND = 0 V, CL = 50 pF
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
WAVEFORMS
Tamb = 0 °C to +70 °C
UNIT
MIN
TYP
MAX
tPERIOD
(parallel
mode)
AV clock period
Figure 36
41.67
ns
tSU
AV clock setup time
Figure 36
4
ns
tIH
AV clock input hold time
Figure 36
3
ns
tOD
AV clock output delay time
Figure 36
3
24
ns
tWHIGH
AV clock pulse width HIGH
Figure 36
10
tWLOW
AV clock pulse width LOW
Figure 36
10
tPWFS
AVxFSYNC pulse width HIGH
Figure 37
200
300
ns
tSUP
PHY-link setup time
Figure 38
6.0
ns
tHP
PHY-link hold time
Figure 38
0
ns
tSCLKPER
SCLK period
Figure 38
20.343
20.345
20.347
ns
tDP
PHY-link output delay
Note: CL = 20 pF
Figure 39
2.0
10.0
ns
tAS
Host address setup time
Figure 40
0
ns
tAH
Host address hold time
Figure 40
2
ns
tCL
Host chip select pulse width LOW
Figure 40
115
ns
tCH
Host chip select pulse width HIGH
Figure 40
42
ns
tRP
Host read pulse width
Figure 40
115
ns
tACC
Host access time
Figure 40
115
ns
tDH
Host data hold time
Figure 40
2
ns
tDS
Host data setup time
Figure 40
0
ns
tDZ
Host data bus release (Hi-Z)
Figure 40
15
ns
tWRP
Host write pulse width
Figure 40
115
ns
tWAIT
WAIT output delay
Figure 40
12
ns
tWWAIT
WAIT pulse width
Figure 40
62
ns
tCWH
CYCLEIN HIGH pulse width
Figure 41
200
ns
tCWL
CYCLEIN LOW pulse width
Figure 41
200
ns
tCP
CYCLEIN cycle period
Figure 41
125
s
tCD
CYCLEOUT cycle delay
Figure 42
20
ns
tRESET
RESET_N pulse width LOW
Figure 43
10
s
tPWALE
ALE pulse width
Figures 8, 9, 10, 11
20
ns
tALES
ALE setup time
Figures 8, 9, 10, 11
3
ns
tALEH
ALE hold time
Figures 8, 9, 10, 11
2
ns
fLPS
LPS signal frequency
–
1.0
2.75
MHz
dcLPS
LPS signal duty cycle
–
23
28
%
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