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參數(shù)資料
| 型號： | 935266671518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144 |
| 封裝： | 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144 |
| 文件頁數(shù)： | 49/83頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 935266671518 |
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Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
50
13.1.4
Link / Phy Interrupt Enable (LNKPHYINTE) – Base Address: 0x00C
This register is a mirror of the Link/Phy Interrupt Acknowledge (LNKPHYINTACK) register. Enabling an interrupt is accomplished by writing a ‘1’
to the bit corresponding to the interrupt desired.
This register enables the interrupts described in the Link /Phy Interrupt Acknowledge register (LNKPHYINTACK) description. A one in any of the
bits enables that function to create an interrupt. A zero disables the interrupt, however the status is readable in the Link /Phy Interrupt
Acknowledge register.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8
7 6
5 4 3
2 1
0
ECMDRST
EF
AIRGAP
EHDRERR
ETCERR
EARBGAP
EPHYINT
ESNT_REJ
EITBADFMT
EA
TBADFMT
EPHYRRX
ECYTMOUT
EPHYRST
ECYDONE
ECYPEND
ECYST
AR
T
ECYSEC
ECYLOST
SV00894
31 30
ETIMER
EAUTH
DN
Reset Value 0x00000000
Bits 21..0 are interrupt enable bits for the Link/Phy Interrupt Acknowledge (LNKPHYINTACK).
13.1.5
Cycle Timer Register (CYCTM) – Base Address: 0x010
Cycle Timer Register operation is controlled by the Cycle Timer Enable (CYTMREN) bit in the Link Control Register (LNKCTL, 0x004). If the
Cycle Timer Register is disabled, it can be used as a general read write register for Host Interface Firmware testing.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CYCLE_SECONDS
CYCLE_NUMBER
CYCLE_OFFSET
SV00276
3130
Reset Value 0x00000000
Bit 31..25:
R/W
Seconds count: 1-Hz cycle timer counter.
Bit 24..12:
R/W
Cycle Number: 8kHz cycle timer counter.
Bit 11..0:
R/W
Cycle Offset: 24.576MHz cycle timer counter.
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