參數(shù)資料
型號： 935266671518
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝： 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁數(shù)： 59/83頁
文件大?。?/td> 316K
代理商： 935266671518
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
59
13.2.11
Isochronous Receiver Interrupt Acknowledge (IRXINTACK) – Base Address: 0x04C
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CIPT
AGFL
T
RCVBP
SQOV
CRCERR
IRXEMPTY
FSYNC
SEQERR
IR512LFT
SV01025
31 30
IR256LFT
IR100LFT
IRO/E
IREMI
IRXFULL
SYT
OVF
Reset Value 0x00000000
Bit 14:
R/W
SYTOVF: SYT FIFO overflow. The isochronous receiver’s SYT field FIFO has overflowed and has been
automatically reset and cleared. This interrupt alerts the host controller that up to 7 AVFSYNC pulses may be
missing due to an SYT field reception error.
Bit 13:
R/W
IRO/E: Odd/even key change. Software should write in the new set of keys to the cipher.
Bit 12:
R/W
IREMI:
This bit indicates when there has been a change in the received EMI bit values (bits 2 and 3 of register
0x054). This interrupt, when = 1, indicates that a changed EMI field has been received.
Bit 10:
R/W
IR100LFT: Interrupt when receiver queue reaches 100 quadlets from full.
Bit 9:
R/W
IR256LFT: Interrupt when receiver queue reaches 256 quadlets from full.
Bit 8:
R/W
IR512LFT: Interrupt when receiver queue reaches 512 quadlets from full. This bit is disabled if 0.5K Byte buffer size
is set.
Bit 7:
R/W
IRXFULL: Isochronous data memory bank has become full. this is a fatal error, the recommended action is to reset
and re-initialize the receiver.
Bit 6:
R/W
IRXEMPTY: Isochronous data memory bank has become empty.
Bit 5:
R/W
FSYNC: Pulse at fsync output.
Bit 4:
R/W
SEQERR: Sequence error of data blocks.
Bit 3:
R/W
CRCERR: CRC error in bus packet.
Bit 2:
R/W
CIPTAGFLT: Faulty CIP header tag (E,F bits). i.e.: The CIP header did not meet the standard and the whole packet
is ignored.
Bit 1:
R/W
RCVBP: Bus packet processing complete.
Bit 0:
R/W
SQOV: Status queue overflow. This is a fatal error, the recommended action is to reset and re-initialize the receiver.
13.2.12
Isochronous Receiver Interrupt Enable (IRXINTE) – Base Address: 0x050
Interrupt enable bits for AV Receiver.
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
ECIPT
AGFL
T
ERCVBP
ESQOV
ECRCERR
EIRXEMPTY
EFSYNC
ESEQERR
EIR512LFT
31 30
SV01026
EIR256LFT
EIR100LFT
EIRO/E
EIREMI
EIRXFULL
ESYTOVF
Reset Value 0x00000000
Bit 13..0 are interrupt enable bits for the Isochronous Receiver Interrupt Acknowledge (IRXINTACK).
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