參數(shù)資料
型號: 935266671518
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 1 CHANNEL(S), 400M bps, SERIAL COMM CONTROLLER, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-486-1, LQFP-144
文件頁數(shù): 40/83頁
文件大?。?/td> 316K
代理商: 935266671518
Philips Semiconductors
Preliminary specification
PDI1394L41
1394 content protection AV link layer controller
2000 Dec 01
42
12.7.1.1
Interrupt Hierarchy
10
18 17 16 15 14 13
9 8 7
6
5 4 3
2 1
0
SV01858
76
5 4 32 10
32 10
ITXINTACK (0x02C)
IRXINTACK (0x04C)
ASYINTACK (0x0A0)
LNKPHYINTACK (0x008)
GLOBCSR (0x018)
HIF INT_N
PHYINT
CMDRST
F
AIRGAP
PHYRRX
ITBADFMT
PHYRST
A
TBADFMT
SNT_REJ
HDRERR
ARBGAP
CYST
AR
T
TCERR
CYTMOUT
CYDONE
CYPEND
CYLOST
CYSEC
INPERR
TRMSYT
TRMBP
DISCARD
ITXFULL
ITXEMPTY
DBCERR
SEQERR
IRXEMPTY
CRCERR
CIPT
AGFL
T
RCVBP
FSYNC
SQOV
ASYTX/RX
ITXINT
IRXINT
LNKPHYINT
16 15 14 13 12 11 10 9 8 7
6
5 4 3
2 1
0
TIMEOUT
RCVDRSP
RRSPQFULL
RREQQFULL
RREQQQA
V
RRSPQRDERR
RREQQRDERR
RRSPQQA
V
SIDQA
V
RREQQLASTQ
TRSPQFULL
RRSPQLASTQ
TREQQWRERR
TRSPQWR
TRSPQWRERR
TREQQFULL
TREQQWR
65 4 3
2 1
0
IRXFULL
8
IR512LFT
9
7
IT512LFT
IT256LFT
8
IR256LFT
IT100LFT
9
20
TIMER
12
IREMI
13
IRO/E
21
AUTH
DN
12
ITEMI
13
IT
O/E
10
IR100LFT
14
M6
ERROR
14
SYT
OVF
NOTE:
1. A read of the RDI register (0xB0) should be done before looking for an interrupt in the GLOBCSR register.
Figure 33.
Interrupt Hierarchy
13.0
REGISTER MAP
Registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. This means that it is not possible to write just the
lower 8 bits, and leave the other bits unaffected (see Section 12.5.2 for more information). The values written to undefined fields/bits are ignored
and thus DON’T CARE.
A full bitmap of all registers is listed in Table 6. The meaning of shading and bit cell values is as follows:
A bit/field with no name written in it and dark shading is reserved and not used.
A bit/field with a name in it and light shading is a READ ONLY (status) bit/field.
A one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset.
Table 6.
Full Bitmap of all Registers (consists of four tables shown on the following pages)
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