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參數(shù)資料
| 型號(hào)： | 935262056518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 尋呼電路 |
| 英文描述： | TELECOM, PAGING DECODER, PQFP32 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32 |
| 文件頁數(shù)： | 9/76頁 |
| 文件大?。?/td> | 301K |
| 代理商： | 935262056518 |
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1999 Apr 12
17
Philips Semiconductors
Product specication
FLEX
roaming decoder II
PCD5013
8.4.3
CONFIGURATION SEQUENCE
A typical configuration and synchronisation sequence
would be as follows, see Fig.11 for event timings:
1. The PCD5013 is reset by the host.
2. After 76800 clock cycles the PCD5013 interrupts the
host to read the part ID by pulling the READY
line LOW.
3. The host pulls SS LOW at the start of each
SPI transfer and clocks out the part ID data.
4. The host configures the following aspects of PCD5013
operation:
a) General configuration (Section 8.4.4)
b) Receiver operation (Section 8.5)
c) FLEX
CAPCODE configuration (Section 8.6).
The PCD5013 writes a part ID packet in response to
each incoming packet.
5. At the end of each packet the PCD5013 pulls the
READY line HIGH, and then LOW again to indicate
that packet processing is complete.
6. The host writes a control packet to enable FLEX
decoding in the PCD5013 (Section 8.4.7).
7. The host writes a checksum packet to enable SPI data
output by the PCD5013 (Section 8.4.2).
8. On recognising a SYNC word, the PCD5013
synchronises to the channel.
9. The PCD5013 initiates an SPI transfer writing the
status packet, indicating that it is now in synchronous
mode.
Fig.11 Typical configuration and synchronization sequence.
handbook, full pagewidth
MBK097
SPI
DECODER-TO-HOST
RESET
READY
SS
FLEX DATASTREAM
SPI
HOST-TO-DECODER
checksum packet (7)
control packet (6)
partid packet (4)
configuration packets
(addresses, receiver etc.)
status packet (9)
partid packet (4)
(1)
(2)
(3)
(5)
(8)
SYNC
Numbers within parenthesis refer to sequence numbers, see Section 8.4.3.
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