參數(shù)資料
型號： 935262056518
廠商： NXP SEMICONDUCTORS
元件分類： 尋呼電路
英文描述： TELECOM, PAGING DECODER, PQFP32
封裝： 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁數(shù)： 62/76頁
文件大小： 301K
代理商： 935262056518
1999 Apr 12
65
Philips Semiconductors
Product specication
FLEX
roaming decoder II
PCD5013
12 DC CHARACTERISTICS
Tamb = 25 to +70 °C; VDD = 2.2 V; f = 76.8 kHz; unless otherwise specied.
Notes
1. External clock signal (frequency = 76.8 kHz, amplitude = VSS to VDD) at pin EXTAL; OSCPD = HIGH;
test inputs = LOW; other inputs = HIGH; outputs unconnected; SPI transmit enabled; COD bit set to logic 1 (see
Section 8.4.4); to obtain the supply current of an application with a crystal connected as in Fig.19, a typical oscillator
current of 2
A needs to be added to this value (see Chapter 14); Tamb = 25 °C.
2. As note 1, but PCD5013 and synchronous to a typical FLEX
data stream (collapse value = 4), Tamb = 25 °C.
13 AC CHARACTERISTICS
Tamb = 25 to +70 °C, VDD = 1.8 to 3.6 V, fEXTAL = 76.8 kHz, maximum load capacitance = 50 pF connected to any
digital output; unless otherwise specied.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDD
supply voltage
1.8
2.2
3.6
V
IDD(stby)
standby supply current
on = 0; note 1
4.9
24
A
IDD
operating supply current
on = 1; note 2
6.0
A
Digital inputs: OSCPD, TEST2, TEST3, RESET, LOBAT, EXTS0, EXTS1, SS and MOSI
VIL
LOW-level input voltage
0.2VDD
V
VIH
HIGH-level input voltage
0.8VDD
V
ILI
LOW/HIGH-level input leakage current
1
A
Digital outputs: MISO, READY, CLKOUT, SYMCLK and S0 to S7
VOL
LOW-level output voltage
Isink = 0.8 mA
0.1
0.4
V
VOH
HIGH-level output voltage
Isource = 0.8 mA
VDD 0.4 VDD 0.1
V
ILO
LOW/HIGH-level output leakage current 3-state outputs
1
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Reset timing
tW(rst)
RESET pulse width
200
ns
tLH(RESET-READY)
RESET LOW to READY HIGH
200
ns
tHL(RESET-READY)
RESET HIGH to READY LOW stable 76.8 kHz clock
1
s
Start-up timing
tstrt(osc)
oscillator start-up time
see Fig.19
0.5
s
th(rst)
RESET hold time
200
ns
tHL(RESET-READY)
RESET HIGH to READY LOW note 1
76800
T
tWUL(osc-READY)
oscillator warmed up to
READY LOW
note 1
76800
T
SPI timing
fSCK
operating frequency
0
1
MHz
Tcy(SCK)
cycle time
1000
ns
tLEAD1
select lead time
200
ns
tLAG1
de-select lag time
200
ns
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