參數(shù)資料
型號(hào): 935262056518
廠商: NXP SEMICONDUCTORS
元件分類(lèi): 尋呼電路
英文描述: TELECOM, PAGING DECODER, PQFP32
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-358-1, LQFP-32
文件頁(yè)數(shù): 26/76頁(yè)
文件大小: 301K
代理商: 935262056518
1999 Apr 12
32
Philips Semiconductors
Product specication
FLEX
roaming decoder II
PCD5013
8.5.6.2
Receiver on setting packets (ID = 16H to 19H)
LBC: low battery check (Tables 24 and 25). If this bit is
set, the PCD5013 checks the status of the LOBAT port just
before leaving this receiver sync setting state. Value after
reset = 0.
CLS: control line setting (Tables 24 and 25). This is the
value to be output on the receiver control lines for this
receiver sync setting state. Value after reset = 0.
ST: step time (Table 24). This sets the waiting time, before
expecting good signals at EXTS1 and EXTS0 at the end of
the warm-up sequence, after turning decoding on.
The setting is in steps of 625
s. Valid values are:
625
s (ST = 01H) to 79.375 ms (ST = 7FH). Value after
reset = 01H.
s: setting number, see Tables 23 and 25 for the s names
and values and location in the receiver on setting packet.
Table 23 s names and values
8.5.7
FORCING RECEIVER LINES (ID = 0FH)
This packet (Table 26) enables host control over the
receiver control line (S0 to S7) settings in all modes except
reset. In reset, the receiver control lines are high
impedance.
FRS: force receiver setting (Table 26). Setting a bit causes
the associated CLS bit in this packet to override the
internal receiver control settings on the corresponding
receiver control line. Clearing a bit returns control of the
corresponding receiver control line to the PCD5013. Value
after reset = 0.
CLS: control line setting (Table 26). This bit setting is
applied to the corresponding receiver control line if the
associated FRS bit is set in this packet. Value after
reset = 0.
s3
s2
s1
s0
SETTING NAME
0111
1600 sps sync
1000
3200 sps data
1001
1600 sps data
Table 24 3200 sps sync setting packet bit assignments
Table 25 Receiver on setting packet bit assignments
Table 26 Receiver line control packet bit assignments
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
300010110
20000
LBC
000
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
00
ST6
ST5
ST4
ST3
ST2
ST1
ST0
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
30001
s3
s2
s1
s0
20000
LBC
000
1
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
000000000
BYTE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
300001111
200000000
1
FRS7
FRS6
FRS5
FRS4
FRS3
FRS2
FRS1
FRS0
0
CLS7
CLS6
CLS5
CLS4
CLS3
CLS2
CLS1
CLS0
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