參數(shù)資料
型號： 9202
廠商： 意法半導(dǎo)體
英文描述： Flash Programmable System Devices with 8032 Microcontroller Core
中文描述： 閃存可編程系統(tǒng)設(shè)備與8032微控制器內(nèi)核
文件頁數(shù)： 88/175頁
文件大?。?/td> 1731K
代理商： 9202
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
88/175
DDC2B Protocol
DDC2B is constructed based on the Philips I
2
C in-
terface. However, in the level of DDC2B, PC host
is fixed as the master and the monitor is always re-
garded as the slave. Both master and slave can be
operated as a transmitter or receiver, but the mas-
ter device determines which mode is activated. In
this protocol, address pointer is also used.
According to DDC2B specification, A0 (for WRITE
Mode) and A1 (for READ Mode) are assigned as
the default address of monitors.
The reception of the incoming data in WRITE
Mode or the updating of the outgoing data in
READ Mode should be finished within the speci-
fied time limit. If software in the slave’s side cannot
react to the master in time, based on I
2
C protocol,
SCL pin can be stretched low to inhibit the further
action from the master. The transaction can be
proceeded in either byte or burst format.
Figure 43. Conceptual Structure of the DDC Interface
AI06645
DDC Interrupt
vector address
( 0023H )
DDC2B/DDC2AB
Utilities
DDC2B
Utilities
DDC1.
DDC2B
Utilities
Check Mode flag in DDCCON
Mode = 1 Mode = 1 Mode = 0
I2C
ServiceRoutines
I2C interface
(H/W)
DDC Transmitter
(H/W)
DDC2B/DDC2AB
commandeceived
DDC2B
SWENB =1
SWENB =0
SWENB =1
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